PE9763
Product Specification
Functional Description
The DSM modulates the “A” counter outputs in
order to achieve the desired fractional step.
The PE9763 consists of counters, a prescaler, an
18-bit delta-sigma modulator (DSM), a phase
detector and a charge pump. The dual modulus
prescaler divides the VCO frequency by either 10
or 11, depending on the value of the modulus
select. Counters “R” and “M” divide the reference
and prescaler output, respectively, by integer
values stored in a 20-bit register. An additional
counter (“A”) is used in the modulus select logic.
The phase-frequency detector generates up and
down frequency control signals. These signals can
be configured to drive a tri-state charge pump.
Data is written into the internal registers via the
three wire serial bus. There are also various
operational and test modes and a lock detect
output
Figure 3. Functional Block Diagram
R Counter
(6-bit)
fr
fc
R(5:0)
M(8:0)
Icp
Charge
Phase
Detector
Sdata
Control
Logic
Pump
K(17:0)
A(3:0)
Control
Pins
PD_U
PD_D
LD
DSM
+
Logic
Modulus
Select
Cext
2 kΩ
Fin
Fin
10/11
Prescaler
M Counter
(9-bit)
fp
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0140-01 │ UltraCMOS™ RFIC Solutions
Page 8 of 15
PSEMI [ Peregrine Semiconductor ]
