PE9763
Product Specification
Figure 4. Serial Interface Mode Timing Diagram
Sdata
E_WR
tEC
tCE
Sclk
S_WR
tDSU
tDHLD
tClkH
tClkL
tCWR
tPW
tWRC
Enhancement Register
The functions of the enhancement register bits are shown below with all bits active “high”.
Table 10. Enhancement Register Bit Functionality
Bit Function
Description
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Reserve **
Reserved.
Reserved.
Reserve **
fp output
Drives the M counter output onto the Dout output.
Power down
Counter load
MSEL output
fc output
Power down of all functions except programming interface.
Immediate and continuous load of counter programming.
Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output.
Drives the reference counter output onto the Dout output.
Disables the LD pin for quieter operation.
LD Disable
** Program to 0
Document No. 70-0140-01 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
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