PE9763
Product Specification
Pin
Valid
Mode
Pin No.
Type
Description
Name
VDD
(Note 1)
(Note 1)
Input
ESD VDD
Prescaler VDD
Prescaler input from the VCO. 3.2 GHz max frequency.
.
46
VDD
Fin
.
Both
Both
47
48
Prescaler complementary input. A bypass capacitor should be placed as close as possible to
this pin and be connected in series with a 50 W resistor directly to the ground plane.
Fin
Input
GND
GND
GND
Downbond
Downbond
Downbond
Prescaler ground.
49
Prescaler ground.
Output driver/charge pump ground.
Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kW series resistor.
Connecting Cext to an external capacitor will low pass filter the input to the inverting amplifier
used for driving LD.
50
51
CEXT
LD
Output
Output
Both
Both
Lock detect and open drain logical inversion of CEXT. When the loop is in lock, LD is high
impedance, otherwise LD is a logic low (“0”).
Both
52
53
54
55
56
57
58
59
DOUT
VDD
Output
(Note 1)
Downbond
Output
Data out function, enabled in enhancement mode.
Output driver/charge pump VDD
.
GND
PD_D
CP
Output driver/charge pump ground.
Both
Both
Both
PD_D pulses down when fp leads fc. PD_U is driven to GND when CPSEL = “High”.
Charge pump output. Selected when CPSEL = “1”. Tristate when CPSEL = “Low”.
PD_U pulses down when fc leads fp. PD_D is driven to GND when CPSEL = “High”.
Output driver/charge pump ground.
Output
PD_U
GND
VDD
Output
Downbond
(Note 1)
Downbond
(Note 1)
(Note 1)
Downbond
Downbond
Input
Output driver/charge pump VDD
.
GND
VDD
Phase detector GND.
Phase detector VDD
.
60
61
VDD
ESD VDD
.
GND
GND
fr
ESD ground.
Reference ground.
Both
62
63
64
Reference frequency input.
Reference VDD
Digital core VDD
Digital core ground.
VDD
(Note 1)
(Note 1)
Downbond
Input
.
VDD
.
GND
ENH
Both
Both
65
66
67
Enhancement mode. When asserted low (“0”), enhancement register bits are functional.
Charge pump select. “High” enables the charge pump and disables pins PD_U and PD_D by
forcing them “low”. A “low” Tri-states the CP and enables PD_U and PD_D.
CPSEL
Input
Input
Both
Both
MS2_SEL
MASH 1-1 select. “High” selects MASH 1-1 mode. “Low” selects the MASH 1-1-1 mode.
K register LSB toggle enable. “1” enables the toggling of LSB. This is equivalent to having
an additional bit for the LSB of K register. The frequency offset as a result of enabling this bit
is the phase detector comparison frequency / 219.
68
RND_SEL
Input
Note 1: All VDD pins are connected by diodes and must be supplied with the same positive voltage level.
Note 2: All digital input pins have 70 kΩ pull-down resistors to ground.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0140-01 │ UltraCMOS™ RFIC Solutions
Page 4 of 15
PSEMI [ Peregrine Semiconductor ]
