PE9763
Product Specification
Table 6. AC Characteristics
VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Control Interface and Latches (see Figures 3, 4)
fClk
tClkH
tClkL
tDSU
tDHLD
tPW
Serial data clock frequency
Serial clock HIGH time
(Note 1)
10
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
30
10
10
30
30
30
30
30
Serial clock LOW time
Sdata set-up time to Sclk rising edge
Sdata hold time after Sclk rising edge
S_WR pulse width
tCWR
tCE
tWRC
tEC
Sclk rising edge to S_WR rising edge
Sclk falling edge to E_WR transition
S_WR falling edge to Sclk rising edge
E_WR transition to Sclk rising edge
Main Divider (Including Prescaler) (Note 4)
Fin
Operating frequency
Input level range
275
-5
3200
5
MHz
dBm
PFin
External AC coupling
Main Divider (Prescaler Bypassed) (Note 4)
Fin
Operating frequency
Input level range
50
-5
300
5
MHz
dBm
PFin
External AC coupling
Reference Divider
(Note 3)
fr
Operating frequency
100
MHz
dBm
Pfr
Reference input power (Note 2)
Single ended input
Phase Detector
(Note 3)
-2
fc
Comparison frequency
50
MHz
SSB Phase Noise (Fin = 1.9 GHz, fr = 20 MHz, fc = 10 MHz, LBW = 50 kHz, VDD = 3.0 V, Temp = 25° C) (Note 4)
Phase Noise
1 kHz Offset
-88
dBc/Hz
dBc/Hz
ΦN
ΦN
Phase Noise
10 kHz Offset
-92
Note 1: fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fclk
specification.
Note 2: CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p. For optimum
phase noise performance, the reference input falling edge rate should be faster than 80mV/ns.
Note 3: Parameter is guaranteed through characterization only and is not tested.
Note 4: Parameter below are not tested for die sales. These parameters are verified during the element evaluation per the die flow.
Document No. 70-0140-01 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 7 of 15
PSEMI [ Peregrine Semiconductor ]
