PE9763
Product Specification
Direct Interface Mode
While the E_WR input is “high” and the S_WR in-
put is “low”, serial input data (Sdata input), B0 to
B7, are clocked serially into the enhancement reg-
ister on the rising edge of Sclk, MSB (B0) first. The
enhancement register is double buffered to pre-
vent inadvertent control changes during serial
loading, with buffer capture of the serially entered
data performed on the falling edge of E_WR ac-
cording to the timing diagram shown in Figure 4.
After the falling edge of E_WR, the data provide
control bits as shown in Table 9 on page 10 will
have their bit functionality enabled by asserting
the Enh input “low”.
Direct Interface Mode is selected by setting the
“Direct” input “high”.
Counter control bits are set directly at the pins as
shown in Table 7 and Table 8.
Table 7. Secondary Register Programming
Interface
Enh R5
R4
M8
M7
Pre_en M6 M5 M4 M3 M2 M1 M0 R3
R2
R1
R0
A3
A2
A1
A0 Addr
Mode
Direct
Serial*
Pre_en
1
1
R5
B0
R4
B1
M8
B2
M7
B3
M6 M5 M4 M3 M2 M1 M0
B5 B6 B7 B8
R3
R2
R1
R0
A3
A2
A1
A0
X
0
B4
B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19
*Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge.
MSB (first in)
(last in) LSB
Table 8. Auxiliary Register Programming
Interface
Enh
K17 K16 K15 K14 K13 K12 K11 K10 K9
K8
K7
K6
K5
K4
K3
K2
K1
K0
Rsrv
Rsrv Addr
Mode
Direct
1
1
K17 K16 K15 K14 K13 K12 K11 K10
B0 B1 B2 B3 B4 B5 B6 B7
K9
B8
K8
K7
K6
K5
K4
K3
K2
K1
K0
X
X
X
1
Serial*
B9 B10 B11 B12 B13 B14 B15 B16 B17
B18
B19
*Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge.
MSB (first in)
(last in) LSB
Table 9. Enhancement Register Programming
Interface
Mode
Power
Down
Counter
load
MSEL
output
fc output
Reserved
Reserved
fp output
LD Disable
Enh
Serial*
0
B0
B1
B2
B3
B4
B5
B6
B7
*Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.
(last in) LSB
MSB (first in)
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0140-01 │ UltraCMOS™ RFIC Solutions
Page 10 of 15
PSEMI [ Peregrine Semiconductor ]
