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9763-01 参数 Datasheet PDF下载

9763-01图片预览
型号: 9763-01
PDF下载: 下载PDF文件 查看货源
内容描述: 3.2 GHz的Δ-Σ调制的分数N频率合成器的低相位噪声应用 [3.2 GHz Delta-Sigma modulated Fractional-N Frequency Synthesizer for Low Phase Noise Applications]
分类和应用:
文件页数/大小: 15 页 / 289 K
品牌: PEREGRINE [ PEREGRINE SEMICONDUCTOR CORP. ]
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PE9763
Product Specification
Pin No.
16
17
18
19
20
21
22
23
24
25
26
27
Pin
Name
K
7
K
8
K
9
K
10
K
11
K
12
K
13
K
14
K
15
K
16
K
17
V
DD
V
DD
GND
Valid
Mode
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
(Note 1)
(Note 1)
Downbond
Downbond
K Counter bit7.
K Counter bit8.
K Counter bit9.
K Counter bit10.
K Counter bit11.
K Counter bit12.
K Counter bit13.
K Counter bit14.
K Counter bit15.
K Counter bit16.
K Counter bit17 (MSB).
Digital core V
DD
.
ESD V
DD
.
Digital core ground.
ESD ground.
M Counter bit0 (LSB).
M Counter bit1.
M Counter bit2
M Counter bit3.
M Counter bit4.
Description
28
GND
29
30
31
32
M
0
M
1
M
2
M
3
M
4
33
S_WR
M
5
34
SDATA
M
6
35
SCLK
36
37
38
M
7
M
8
A
0
A
1
39
E_WR
40
41
42
43
44
45
GND
Downbond
ESD ground.
A
2
A
3
DIRECT
Pre_en
V
DD
GND
Direct
Direct
Direct
Direct
Direct
Serial
Direct
Serial
Direct
Serial
Direct
Direct
Direct
Direct
Serial
Direct
Direct
Both
Direct
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
(Note 1)
Downbond
Serial load enable input. While S_WR is “low”, Sdata can be serially clocked. Primary register
data are transferred to the secondary register on S_WR or Hop_WR rising edge.
M Counter bit5.
Binary serial data input. Input data entered MSB first.
M Counter bit6.
Serial clock input. SDATA is clocked serially into the 20-bit primary register (E_WR “low”) or
the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk.
M Counter bit7.
M Counter bit8 (MSB).
A Counter bit0 (LSB).
A Counter bit1.
Enhancement register write enable. While E_WR is “high”, Sdata can be serially clocked into
the enhancement register on the rising edge of Sclk.
A Counter bit2.
A Counter bit3 (MSB).
Direct mode select. “High” enables direct mode. “Low” enables serial mode.
Prescaler enable, active “low”. When “high”, Fin bypasses the prescaler.
Digital core V
DD
.
Digital core ground.
Document No. 70-0140-01
www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
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