OXCB950
OXFORD SEMICONDUCTOR LTD.
6.8 Cardbus Tuple Information
; Tuple Data for: (CISTPL_LINKTARGET)
13 03
43 49 53
The cardbus information structure exists in the PCI
configuration space at the user selectable location of either
DWORD 18 or DWORD 32 and can occupy the entire PCI
configuration space region from these specified locations
upto DWORD 63.
; Tuple Data for: (CISTPL_MANFID)
20 04
79 02 01 00
; Tuple Data for: (CISTPL_CONFIG_CB)
By default, the Tuple information contained within the
cardbus information structure (CIS) has been hardcoded
into the device and has been designed to satisfy the
requirements for most serial port based cardbus
applications.
04 06
03 00 05 00 00 00
; Tuple Data for: (CISTPL_BAR)
07 06
11 00 F8 FF FF FF
For those manufacturers who would prefer to utilise their
own tuple information into the cardbus information
structure, for example to change the product ID and
Manufacturers ID codes, then a facility is available that
switches tuple access from the hardcoded area to a RAM
that contains the user defined tuple information. Using the
optional EEPROM to download data into the “CIS zone”
results in the user defined tuple data being downloaded
into this RAM and the RAM contents being then presented
to the configuration software, once the OXCB950 device
accepts the cardbus configuration accesses.
; Tuple Data for: (CISTPL_BAR)
07 06
02 00 00 F0 FF FF
; Tuple Data for: (CISTPL_BAR)
07 06
13 00 F0 FF FF FF
; Tuple Data for: (CISTPL_BAR)
07 06
04 00 00 F0 FF FF
The size of the RAM is 46 x 32bit data. This allows up to
184 bytes of Tuple information to be present in the PCI
configuration space (from Dword18 to Dword63).
; Tuple Data for: (CISTPL_BAR)
07 06
05 00 00 F0 FF FF
By default, this RAM is set to read-only for configuration
accesses. However, it is possible to enable configuration
writes to this RAM by enabling the local configuration
register LCC, bit 22 either through the EEPROM when
downloading into the CIS zone or via transactions to this
register bit. Only configuration writes will be possible to this
RAM for experimentation purposes. Any new tuple data
written directly into the RAM using cardbus transactions will
not be automatically transferred to the EEPROM for
subsequent downloads. The EEPROM will need to be
updated using the controls in the local configuration
register LCC, to mirror the data written directly to the RAM.
; Tuple Data for: (CISTPL_CFTABLE_ENTRY_CB)
05 0C
40 B9 29 B5 1E 02 30 FF FF 04 C0 00
; Tuple Data for: (CISTPL_VERS_1)
15 18
07 01 4F 58 53 45 4D 49 00 4F 58 43 42 39 35 30
00 52 65 76 20 41 00 FF
; Tuple Data for: (CISTPL_FUNCID)
21 02
02 00
The hardcoded (default) values in the cardbus information
structure are as follows. This is the listing provided by
Microsofts Tuple Utility DTPL.exe when operating on the
Tuple information.
; Tuple Data for: (CISTPL_FUNCE)
22 04
00 02 0F 7F
NOTE : For user defined tuples, the tuple
; Tuple Data for: (CISTPL_DEVICE_OC)
CISTPL_CONFIG_CB must indicate the cardbus status
registers to be located at the (PCI) BAR4 in the PCI
configuration space. PCI specifications define the base
addresses as BAR0 0 – BAR5. Cardbus specifications
define the base addresses as BAR1 – BAR6.
1C 04
02 D2 08 FF
; Tuple Data for: (CISTPL_END)
FF FF (None)
DS-0033 Sep 05
External-Free Release
Page 27
OXFORD [ OXFORD SEMICONDUCTOR ]
