µPD703100A-33, 703100A-40, 703101A-33, 703102A-33
(5/7)
Execution
Flags
Clock
Mnemonic
SATADD
Operand
Opcode
Operation
i
r
l
CY OV
S
×
×
Z
×
×
SAT
×
reg1,reg2
rr r r r 0 0 0 1 1 0 R R R R R GR[reg2]←saturated(GR[reg2]+GR[reg1])
1
1
1
1
1
1
×
×
×
×
imm5,reg2
rr r r r 0 1 0 0 0 1 i i i i i GR[reg2]←saturated(GR[reg2]+sign-
×
extend(imm5)
SATSUB
SATSUBI
reg1,reg2
rr r r r 0 0 0 1 0 1 R R R R R GR[reg2]←saturated(GR[reg2]−GR[reg1])
1
1
1
1
1
1
×
×
×
×
×
×
×
×
×
×
imm16,reg1,reg2 rr r r r 1 1 0 0 1 1 R R R R R GR[reg2]←saturated(GR[reg1]−sign-
ii i i i i i i i i i i i i i i extend(imm16)
SATSUBR reg1,reg2
rr r r r 0 0 0 1 0 0 R R R R R GR[reg2]←saturated(GR[reg1]−GR[reg2])
rr r r r 1 1 1 1 1 1 0 c c c c If conditions are satisfied
1
1
1
1
1
1
×
×
×
×
×
SETF
cccc,reg2
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 then GR[reg2] 00000001H
←
else GR[reg2]←00000000H
SET1
bit#3,disp16[reg1] 00 b b b 1 1 1 1 1 0 R R R R R adr←GR[reg1]+sign-extend(disp16)
3
3
3
×
×
dd d d d d d d d d d d d d d d Z flag Not(Load-memory-bit(adr,bit#3))
Note 3 Note 3 Note 3
←
Store-memory-bit(adr,bit#3,1)
reg2,[reg1]
rr r r r 1 1 1 1 1 1 R R R R R adr←GR[reg1]
3
3
3
00 0 0 0 0 0 0 1 1 1 0 0 0 0 0 Z flag Not(Load-memory-bit(adr,reg2))
Note 3 Note 3 Note 3
←
Store-memory-bit(adr,reg2,1)
SHL
SHR
reg1,reg2
rr r r r 1 1 1 1 1 1 R R R R R GR[reg2]←GR[reg2] logically shift left by
1
1
1
1
1
1
1
1
1
1
1
1
1
1
×
×
×
×
0
0
0
0
×
×
×
×
×
×
×
×
GR[reg1]
0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0
imm5,reg2
reg1,reg2
rr r r r 0 1 0 1 1 0 i i i i i GR[reg2]←GR[reg2] logically shift left by
zero-extend(imm5)
rr r r r 1 1 1 1 1 1 R R R R R GR[reg2]←GR[reg2] logically shift right by
GR[reg1]
0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
imm5,reg2
disp7[ep],reg2
rr r r r 0 1 0 1 0 0 i i i i i GR[reg2]←GR[reg2] logically shift right by
zero-extend(imm5)
SLD.B
rr r r r 0 1 1 0 d d d d d d d adr←ep+zero-extend(disp7)
GR[reg2]←sign-extend(Load-
n
Note 9
memory(adr,Byte))
SLD.BU
SLD.H
disp4[ep],reg2
rr r r r 0 0 0 0 1 1 0 d d d d adr←ep+zero-extend(disp4)
GR[reg2]←zero-extend(Load-
1
1
1
1
1
1
n
Note 9
Note 18
memory(adr,Byte))
disp8[ep],reg2
rr r r r 1 0 0 0 d d d d d d d adr←ep+zero-extend(disp8)
n
GR[reg2]←sign-extend(Load-
Note 9
Note 19
memory(adr,Half-word))
SLD.HU
disp5[ep],reg2
rr r r r 0 0 0 0 1 1 1 d d d d adr←ep+zero-extend(disp5)
GR[reg2]←zero-extend(Load-
n
Note 9
Notes 18, 20
memory(adr,Half-word))
SLD.W
SST.B
disp8[ep],reg2
rr r r r 1 0 1 0 d d d d d d 0 adr←ep+zero-extend(disp8)
1
1
1
1
n
GR[reg2]←Load-memory(adr,Word))
Note 9
Note 21
reg2,disp7[ep]
rr r r r 0 1 1 1 d d d d d d d adr←ep+zero-extend(disp7)
1
Store-memory(adr,GR[reg2],Byte)
64
Preliminary Data Sheet U14168EJ2V0DS00
NEC [ NEC ]
