µPD703100A-33, 703100A-40, 703101A-33, 703102A-33
Capacitance (TA = 25°C, VDD = HVDD = CVDD = VSS = 0 V)
Parameter
Input capacitance
Symbol
CI
Condition
MIN.
TYP.
MAX.
15
Unit
pF
fc = 1 MHz
Unmeasured pins returned to 0 V.
Input/output capacitance
Output capacitance
CIO
pF
15
CO
pF
15
Operating Conditions
Operation
Mode
Operating Ambient
Temperature (TA)
Power Supply Voltage
(VDD, HVDD)
Internal Operating Clock Frequency (φ)
Direct mode
µPD703100A-40
2 to 40 MHz
−40 to +70°C
−40 to +85°C
−40 to +85°C
−40 to +70°C
−40 to +85°C
−40 to +85°C
3.0 to 3.6 V
µPD703100A-33
2 to 33 MHz
µPD703101A-33, 703102A-33
µPD703100A-40
10 to 33 MHz
2 to 40 MHzNote 1
2 to 33 MHzNote 2
20 to 33 MHzNote 2
PLL mode
µPD703100A-33
µPD703101A-33, 703102A-33
Notes 1. The input clock frequency used in PLL mode should be 4.0 to 8.0 MHz.
2. The input clock frequency used in PLL mode should be used by 4.0 to 6.6 MHz.
68
Preliminary Data Sheet U14168EJ2V0DS00
NEC [ NEC ]
