µPD703100A-33, 703100A-40, 703101A-33, 703102A-33
(2/7)
Execution
Flags
Clock
Mnemonic
DISPOSE
Operand
Opcode
Operation
i
r
l
CY OV
S
Z
SAT
00 0 0 0 1 1 0 0 1 i i i i i L
LL L L L L L L L L L 0 0 0 0 0
imm5,list12
sp←sp+zero-extend(imm5 logically shift left N+1 N+1 N+1
by 2)
Note 4 Note 4 Note 4
GR[reg in list12]←Load-memory(sp,Word)
sp←sp+4
repeat 2 steps above until all regs in list12
is loaded
imm5,list12,[reg1] 00 0 0 0 1 1 0 0 1 i i i i i L sp←sp+zero-extend(imm5 logically shift left N+3 N+3 N+3
by 2)
Note 4 Note 4 Note 4
LL L L L L L L L L L R R R R R
GR[reg in list12]←Load-memory(sp,Word)
Note 5
sp←sp+4
repeat 2 steps above until all regs in list 12
is loaded
PC←GR[reg1]
DIV
reg1,reg2,reg3
rr r r r 1 1 1 1 1 1 R R R R R GR[reg2]←GR[reg2]÷GR[reg1]
35 35 35
w w w w w 0 1 0 1 1 0 0 0 0 0 0 GR[reg3] GR[reg2]%GR[reg1]
←
DIVH
reg1,reg2
r r r r r 0 0 0 0 1 0 R R R R R GR[reg2]←GR[reg2]÷GR[reg1] Note 6
r r r r r 1 1 1 1 1 1 R R R R R GR[reg2]←GR[reg2]÷GR[reg1] Note 6
35 35 35
35 35 35
×
×
×
×
×
×
reg1,reg2,reg3
w w w w w 0 1 0 1 0 0 0 0 0 0 0 GR[reg3] GR[reg2]%GR[reg1]
←
DIVHU
DIVU
EI
reg1,reg2,reg3
reg1,reg2,reg3
r r r r r 1 1 1 1 1 1 R R R R R GR[reg2]←GR[reg2]÷GR[reg1] Note 6
34 34 34
34 34 34
×
×
×
×
×
×
w w w w w 0 1 0 1 0 0 0 0 0 1 0 GR[reg3] GR[reg2]%GR[reg1]
←
r r r r r 1 1 1 1 1 1 R R R R R GR[reg2]←GR[reg2]÷GR[reg1]
w w w w w 0 1 0 1 1 0 0 0 0 1 0 GR[reg3] GR[reg2]%GR[reg1]
←
10 0 0 0 1 1 1 1 1 1 0 0 0 0 0 PSW.ID←0
1
1
1
1
1
1
1
1
1
00 0 0 0 0 0 1 0 1 1 0 0 0 0 0
HALT
HSW
00 0 0 0 1 1 1 1 1 1 0 0 0 0 0 Stop
00 0 0 0 0 0 1 0 0 1 0 0 0 0 0
reg2,reg3
rr r r r 1 1 1 1 1 1 0 0 0 0 0 GR[reg3]←GR[reg2] (15 : 0) II GR[reg2]
×
0
×
×
(31: 16)
w w w w w 0 1 1 0 1 0 0 0 1 0 0
JARL
disp22,reg2
rr r r r 1 1 1 1 0 d d d d d d GR[reg2]←PC+4
2
2
2
PC←PC+sign–extend(disp22)
dd d d d d d d d d d d d d d 0
Note 7
JMP
JR
[reg1]
00 0 0 0 0 0 0 0 1 1 R R R R R PC←GR[reg1]
3
2
3
2
3
2
00 0 0 0 1 1 1 1 0 d d d d d d
dd d d d d d d d d d d d d d 0
Note 7
disp22
PC←PC+sign-extend(disp22)
LD.B
disp16[reg1],reg2 rr r r r 1 1 1 0 0 0 R R R R R adr←GR[reg1]+sign-extend(disp16)
1
1
n
GR[reg2]←sign-extend(Load-memory
Note 9
dd d d d d d d d d d d d d d d
(adr,Byte))
61
Preliminary Data Sheet U14168EJ2V0DS00
NEC [ NEC ]
