µPD703100A-33, 703100A-40, 703101A-33, 703102A-33
(4/7)
Execution
Flags
Clock
Mnemonic
MULU
Operand
Opcode
Operation
i
r
l
CY OV
S
Z
SAT
GR[reg3] II GR[reg2]
GR[reg2] GR[reg1]
← ×
reg1,reg2,reg3
imm9,reg2,reg3
rr r r r 1 1 1 1 1 1 R R R R R
w w w w w 0 1 0 0 0 1 0 0 0 1 0
1
2
2
Note 14
r r r r r 1 1 1 1 1 1 i i i i i GR[reg3] II GR[reg2]←GR[reg2] × zero-
1
2
2
ww w w w 0 1 0 0 1 1 1 1 1 1 0 extend(imm9)
Note 13
Note 14
NOP
NOT
NOT1
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Pass at least one clock cycle doing nothing
rr r r r 0 0 0 0 0 1 R R R R R GR[reg2]←NOT(GR[reg1])
1
1
3
1
1
3
1
1
3
reg1,reg2
0
×
×
×
bit#3,disp16[reg1] 01 b b b 1 1 1 1 1 0 R R R R R adr←GR[reg1]+sign-extend(disp16)
dd d d d d d d d d d d d d d d Z flag Not(Load-memory-bit(adr,bit#3))
Note 3 Note 3 Note 3
←
Store-memory-bit(adr,bit#3,Z flag)
reg2,[reg1]
reg1,reg2
rr r r r 1 1 1 1 1 1 R R R R R adr←GR[reg1]
3
3
3
×
Z flag←Not(Load-memory-bit(adr,reg2))
Note 3 Note 3 Note 3
00 0 0 0 0 0 0 1 1 1 0 0 0 1 0
Store-memory-bit(adr,reg2,Z flag)
OR
rr r r r 0 0 1 0 0 0 R R R R R GR[reg2]←GR[reg2] OR GR[reg1]
1
1
1
1
1
1
0
0
×
×
×
×
ORI
imm16,reg1,reg2 rr r r r 1 1 0 1 0 0 R R R R R GR[reg2]←GR[reg1] OR zero-
ii i i i i i i i i i i i i i i extend(imm16)
PREPARE list12,imm5
00 0 0 0 1 1 1 1 0 i i i i i L Store-memory(sp-4,GR[reg in list12],Word) N+1 N+1 N+1
LL L L L L L L L L L 0 0 0 0 1 sp sp-4
Note 4 Note 4 Note 4
←
repeat 1 step above until all regs in list12 is
stored sp←sp-zero-extend(imm5)
list12,imm5,
00 0 0 0 1 1 1 1 0 i i i i i L Store-memory(sp-4,GR[reg in list12],Word) N+2 N+2 N+2
sp/immNote 15
LL L L L L L L L L L f f 0 1 1 sp←sp-4
Note 4 Note 4 Note 4
imm16/imm32
repeat 1 step above until all regs in list12 is Note 17 Note 17 Note 17
Note 16 stored sp←sp-zero-extend(imm5)
ep←sp/imm
RETI
00 0 0 0 1 1 1 1 1 1 0 0 0 0 0 if PSW.EP=1
then PC
3
3
3
R
R
R
R
R
←EIPC
00 0 0 0 0 0 1 0 1 0 0 0 0 0 0
PSW
←EIPSW
else if PSW.NP = 1
then
else
PC
PSW ←FEPSW
PC
←EIPC
PSW ←EIPSW
←FEPC
SAR
reg1,reg2
imm5,reg2
cccc,reg2
rr r r r 1 1 1 1 1 1 R R R R R GR[reg2]←GR[reg2]arithmetically shift right
0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 by GR[reg1]
1
1
1
1
1
1
1
1
1
×
×
0
0
×
×
×
×
rr r r r 0 1 0 1 0 1 i i i i i GR[reg2]←GR[reg2]arithmetically shift right
by zero-extend(imm5)
SASF
rr r r r 1 1 1 1 1 0 c c c c c if conditions are satisfied
00 0 0 0 0 1 0 0 0 0 0 0 0 0 0 then GR[reg2] (GR[reg2] Logically shift
←
left by 1)
OR 00000001H
else GR[reg2]←(GR[reg2] Logically shift
left by 1)
OR 00000000H
63
Preliminary Data Sheet U14168EJ2V0DS00
NEC [ NEC ]
