µPD703100A-33, 703100A-40, 703101A-33, 703102A-33
(6/7)
Execution
Flags
Clock
Mnemonic
Operand
Opcode
Operation
i
r
l
CY OV
S
Z
SAT
SST.H
SST.W
ST.B
reg2,disp8[ep]
reg2,disp8[ep]
rr r r r 1 0 0 1 d d d d d d d adr←ep+zero-extend(disp8)
Note 19 Store-memory(adr,GR[reg2],Half-word)
1
1
1
rr r r r 1 0 1 0 d d d d d d 1 adr←ep+zero-extend(disp8)
Note 21 Store-memory(adr,GR[reg2],Word)
1
1
1
1
1
1
1
1
1
reg2,disp16[reg1] rr r r r 1 1 1 0 1 0 R R R R R adr←GR[reg1]+sign-extend(disp16)
Store-memory(adr,GR[reg2],Byte)
dd d d d d d d d d d d d d d d
ST.H
reg2,disp16[reg1] rr r r r 1 1 1 0 1 1 R R R R R adr←GR[reg1]+sign-extend(disp16)
dd d d d d d d d d d d d d d 0 Store-memory(adr,GR[reg2],Half-word)
Note 8
ST.W
STSR
reg2,disp16[reg1] rr r r r 1 1 1 0 1 1 R R R R R adr←GR[reg1]+sign-extend(disp16)
dd d d d d d d d d d d d d d 1 Store-memory(adr,GR[reg2],Word)
Note 8
1
1
1
1
1
1
regID,reg2
rr r r r 1 1 1 1 1 1 R R R R R GR[reg2]←SR[regID]
00 0 0 0 0 0 0 0 1 0 0 0 0 0 0
SUB
reg1,reg2
reg1,reg2
reg1
rr r r r 0 0 1 1 0 1 R R R R R GR[reg2]←GR[reg2]−GR[reg1]
rr r r r 0 0 1 1 0 0 R R R R R GR[reg2]←GR[reg1]−GR[reg2]
1
1
5
1
1
5
1
1
5
×
×
×
×
×
×
×
×
SUBR
SWITCH
00 0 0 0 0 0 0 0 1 0 R R R R R adr←(PC+2)+(GR[reg1] logically shift left
by 1)
PC←(PC+2)+(sign-extend(Load-
memory(adr,Half-word)))
logically shift left by 1
SXB
reg1
00 0 0 0 0 0 0 1 0 1 R R R R R GR[reg1]←sign-extend
1
1
3
1
1
3
1
1
3
(GR[reg1] (7 : 0)
SXH
TRAP
reg1
00 0 0 0 0 0 0 1 1 1 R R R R R GR[reg1]←sign-extend
(GR[reg1] (15 : 0))
vector
00 0 0 0 1 1 1 1 1 1 i i i i i EIPC
00 0 0 0 0 0 1 0 0 0 0 0 0 0 0 EIPSW
←PC+4 (restore PC)
PSW
←
ECR.EICC
←Interrupt code
←1
PSW.EP
PSW.ID
PC
←1
←00000040H (when vector
is 00H to 0FH)
00000050H (when vector
is 10H to 1FH)
TST
reg1,reg2
rr r r r 0 0 1 0 1 1 R R R R R result←GR[reg2] AND GR[reg1]
1
3
1
3
1
3
0
×
×
×
TST1
bit#3,disp16[reg1] 11 b b b 1 1 1 1 1 0 R R R R R adr←GR[reg1]+sign-extend(disp16)
dd d d d d d d d d d d d d d d Z flag Not(Load-memory-bit(adr,bit#3))
Note 3 Note 3 Note 3
←
reg2,[reg1]
rr r r r 1 1 1 1 1 1 R R R R R adr←GR[reg1]
3
3
3
×
00 0 0 0 0 0 0 1 1 1 0 0 1 1 0 Z flag Not(Load-memory-bit(adr,reg2))
Note 3 Note 3 Note 3
←
65
Preliminary Data Sheet U14168EJ2V0DS00
NEC [ NEC ]
