µPD703100A-33, 703100A-40, 703101A-33, 703102A-33
Instruction Set
(1/7)
Execution
Flags
Clock
Mnemonic
Operand
Opcode
Operation
i
r
l
CY OV
S
×
×
×
Z
×
×
×
SAT
rr r r r 0 0 1 1 1 0 R R R R R
ADD
reg1,reg2
imm5,reg2
GR[reg2]←GR[reg2]+GR[reg1]
1
1
1
1
1
1
1
1
1
×
×
×
×
×
×
rr r r r 0 1 0 0 1 0 i i i i i GR[reg2] GR[reg2]+sign-extend(imm5)
←
ADDI
imm16,reg1,reg2 r r r r r 1 1 0 0 0 0 r r r r r GR[reg2]←GR[reg1]+sign-extend(imm16)
i i ii i i i i i i i i i i i i
AND
reg1,reg2
rr r r r 0 0 1 0 1 0 R R R R R GR[reg2]←GR[reg2]AND GR[reg1]
1
1
1
1
1
1
0
0
×
×
×
ANDI
imm16,reg1,reg2 rr r r r 1 1 0 1 1 0 R R R R R GR[reg2]←GR[reg1]AND zero-
0
extend(imm16)
ii i i i i i i i i i i i i i i
dd d d d 1 0 1 1 d d d c c c c
2
Bcond
disp9
if conditions are satisfied
then PC ← PC+sign-
extend(disp9)
When
2
2
conditions are Note 2 Note 2 Note 2
Note 1
satisfied
When
1
1
1
conditions are
not satisfied
GR[reg3]
←
GR[reg2] (23 : 16) II GR[reg2]
BSH
reg2,reg3
reg2,reg3
imm6
rr r r r 1 1 1 1 1 1 0 0 0 0 0
ww w w w 0 1 1 0 1 0 0 0 0 1 0
1
1
4
1
1
4
1
1
4
×
×
0
0
×
×
×
×
(31 : 24) II GR[reg2] (7 : 0) II GR[reg2] (15 : 8)
GR[reg3]
←
GR[reg2] (7 : 0) II GR[reg2] (15 : 8) II
BSW
CALLT
rr r r r 1 1 1 1 1 1 0 0 0 0 0
ww w w w 0 1 1 0 1 0 0 0 0 0 0
GR[reg2] (23 : 16) II GR[reg2] (31 : 24)
00 0 0 0 0 1 0 0 0 i i i i i i CTPC←PC+2(return PC)
CTPSW←PSW
adr←CTBP+zero-extend(imm6 logically
shift left by 1)
PC←CTBP+zero-extend(Load-
memory(adr, Half-word))
CLR1
CMOV
CMP
bit#3,
10 b b b 1 1 1 1 1 0 R R R R R adr←GR[reg1]+sign-extend(disp16)
3
3
3
×
×
disp 16[reg1]
Z flags←Not(Load-memory-bit(adr,bit#3))
Note 3 Note 3 Note 3
dd d d d d d d d d d d d d d d
Store-memory-bit (adr,bit#3,0)
reg2,[reg1]
rr r r r 1 1 1 1 1 1 R R R R R adr←GR[reg1]
Z flags←Not(Load-memory-bit(adr,reg2))
3
3
3
Note 3 Note 3 Note 3
00 0 0 0 0 0 0 1 1 1 0 0 1 0 0
Store-memory-bit (adr,reg2,0)
cccc,imm5,reg2,
reg3
rr r r r 1 1 1 1 1 1 i i i i i if condition are satisfied then
1
1
1
1
1
1
GR[reg3]←sign-extended(imm5)
else GR[reg3]←GR[reg2]
ww w w w 0 1 1 0 0 0 c c c c 0
cccc,reg1,reg2,
reg3
rr r r r 1 1 1 1 1 1 R R R R R if conditions are satisfied
then GR[reg3]←GR[reg1]
else GR[reg3]←GR[reg2]
ww w w w 0 1 1 0 0 1 c c c c 0
reg1,reg2
rr r r r 0 0 1 1 1 1 R R R R R result←GR[reg2]−GR[reg1]
1
1
3
1
1
3
1
1
3
×
×
×
×
×
×
×
×
rr r r r 0 1 0 0 1 1 i i i i i result GR[reg2] sign-extend(imm5)
imm5,reg2
←
−
CTRET
DI
00 0 0 0 1 1 1 1 1 1 0 0 0 0 0 PC←CTPC
R
R
R
R
R
00 0 0 0 0 0 1 0 1 0 0 0 1 0 0 PSW CTPSW
←
00 0 0 0 1 1 1 1 1 1 0 0 0 0 0 PSW.ID←1
1
1
1
00 0 0 0 0 0 1 0 1 1 0 0 0 0 0
60
Preliminary Data Sheet U14168EJ2V0DS00
NEC [ NEC ]
