MU9C4480A/L
INSTRUCTION SET DESCRIPTIONS* Continued
Skipped, or Random entries against the Comparand register
through a mask register, if one is selected. During a CMP E
instruction, the compare is only done on the Validity bits
and all data bits are automatically masked.
Instruction: Temporary Command Override (TCO)
Binary Op-Code: 0000 0010 00dd d000
ddd
Register selected as source or
destination for only the next
Command Read or Write cycle
Instruction: Special Instructions
Binary Op-Code: 0000 0110 00dd drrr
The TCO instruction selects a register as the source or
destination for only the next Command Read or Write cycle,
so a value can be loaded or read out of the register. Subsequent
Command Read or Write Cycles revert to reading the Status
register and writing to the Instruction decoder. All registers
but the NF, PS, and PD can be written to, and all can be read
from. The Status register is only available via non-TCO
Command Read cycles. Reading the PS register also outputs
the Device ID on bits 15–4 as shown in Table 12 on page 21.
ddd
rrr
Target resource
Operation
These instructions are a special set for the LANCAM to
accommodate the added features over the MU9C1480. Two
alternate sets of configuration registers can be selected by
using the Select Foreground and Select Background
Registers instructions. These registers are the Control,
Segment Control, Address, Mask Register 1, and the PS
and PD registers. An RSC instruction resets the Segment
Control register count values for both the Destination and
Source counters to the original Start limits. The Shift
instructions shift the designated register one bit right or
left. The right and left limits for shifting are determined by
the CAM/RAM partitioning set in the Control register. The
Comparand register is a barrel-shifter, and for the example
of a device set to 64 bits of CAM executing a Shift
Comparand Right instruction, bit 0 is moved to bit 63, bit 1
is moved to bit 0, and bit 63 is moved to bit 62. For a Shift
Comparand Left instruction, bit 63 is moved to bit 0, bit 0 is
moved to bit 1, and bit 62 is moved to bit 63. MR2 acts as a
sliding mask, where for a Shift Right instruction bit 1 is
moved to bit 0, while bit 0 “falls off the end,” and bit 63 is
replicated to bit 62. For a Shift Mask Left instruction, bit 0 is
replicated to bit 1, bit 62 is moved to bit 63, and bit 63 “falls off
the end.” With shorter width CAM fields, the bit limits on the
right or left move to match the width of CAM field.
Instruction: Data Move (MOV)
Binary Op-Code: 0000 f011 mmdd dsss or
0000 f011 mmdd dvss
f
Address Field flag†
Mask Register select
Destination of data
Source of data
Validity setting if destination is a
Memory location
mm
ddd
sss
v
The MOV instruction performs a 64-bit move of the data in the
selected source to the selected destination. If the source or
destination is aaaH, the Address register is set to “aaaH.” For
MOV instructions to or from aaaH or [AR], the Address
register will increment or decrement from that value after the
move completes, as set in the Control register. Data transfers
between the Memory array and the Comparand register may
be masked by either Mask Register 1 or Mask Register 2, in
which case, only those bits in the destination which correspond
to bits in the selected mask register set to 0 will be changed. A
Memory location used as a destination for a MOV instruction
maybesettoValidorleftunchanged. Ifthesourceanddestination
are the same register, no net change occurs (a NOP).
Instruction: Set Full Flag (SFF)
Binary Op-Code: 0000 0111 0000 0000*
The SFF instruction is a special instruction used to force
the Full flag LOW to permit setting the Page Address
register in vertically cascaded systems.
Instruction: Validity Bit Control (VBC)
Binary Op-Code: 0000 f100 00dd dvvv
Instruction: No Operation (NOP)
f
Address Field flag†
Binary Op-Code: 0000 0011 0000 0000
The NOP (No-OP) belongs to the MOV instructions, where
a register is moved to itself. No change occurs within the
device. This instruction is useful in unlocking the daisy
chain in Standard mode.
ddd
vvv
Destination of data
Validity setting for Memory location
The VBC instruction sets the Validity bits at the selected
memory locations to the selected state. This feature can be
used to find all valid entries by using a repetitive sequence
of CMP V through a ms of all 1s followed by a VBC HM, S.
If the VBC target is aaaH, the Address register is set to
“aaaH.” For VBC instructions to or from aaaH or [AR], the
Addressregisterwillincrementordecrementfromthatvalueafter
the operation completes, as set in the Control register.
Notes:
* Instruction cycle lengths given in Table 7 on page 20.
† If f=1, the instruction requires an absolute address to be supplied on
the following cycle as a Command write. The value supplied on the
second cycle of the instruction will update the Address register. After
operations involving M@[AR] or M@aaaH, the Address register will
increment or decrement depending on the setting in the Control register.
Instruction: Compare (CMP)
Binary Op-Code: 0000 0101 0000 0vvv
vvv
Validity condition
A CMP V, S, or R instruction forces a Comparison of Valid,
17
Rev. 3a
MUSIC [ MUSIC SEMICONDUCTORS ]
