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MU9C4480A-12DC 参数 Datasheet PDF下载

MU9C4480A-12DC图片预览
型号: MU9C4480A-12DC
PDF下载: 下载PDF文件 查看货源
内容描述: [Content Addressable SRAM, 4KX64, 85ns, CMOS, PQCC44]
分类和应用: 局域网双倍数据速率静态存储器内存集成电路
文件页数/大小: 28 页 / 143 K
品牌: MUSIC [ MUSIC SEMICONDUCTORS ]
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MU9C4480A/L  
OPERATIONAL CHARACTERISTICS Continued  
The ripple delay of the flags when connected in a daisy  
chain requires the extension of the /E HIGH time until the  
logic in all devices has settled out. In a string of “n” devices,  
the /E HIGH time should be greater than  
Highest-Priority Match device will respond to any cycle,  
such as an associated data or Status Register read. If there  
is not a match, then a NOP with /EC HIGH needs to be  
inserted before issuing any new instructions, such as Write  
to Next Free Address instruction to learn the data. Since  
Next Free operations are controlled by the /FI–/FF daisy  
chain, only the device with the first empty location will  
respond. If an instruction is used to unlock the daisy chain  
it will work only on the Highest-Priority Match device, if  
one exists. If none exists, the instruction will have no effect  
except to unlock the daisy chain. To read the Status  
registers of specific devices when there is no match requires  
the use of the TCO DS command to set DS=PA of each  
device. Single chip systems can tie /EC HIGH and read the  
Status register or the /MA and /MM pins to monitor match  
conditions, as the daisy chain lock-out feature is not needed  
in this configuration. This removes the need to insert a  
NOP in the case of a no-match.  
tEHMFV + (n-2)· tMIVMFV  
If the last device’s Match flag is required by external logic or a  
state machine before the start of the next CAM cycle, one  
additional tMIVMFV should be added to the /E HIGH time  
along with the setup time and delays for the external logic.  
Locked Daisy Chain  
In a locked daisy chain, the highest-priority device is the  
one with /MI HIGH and /MF LOW. In the Standard mode,  
only this device will respond to command and data reads  
and writes, until the daisy chain has been unlocked by  
taking /EC HIGH. This allows reading the associated data  
field from only the Highest-Priority Match location  
anywhere in a string of devices, or the Match address from  
the Status register of the device with the match. It also  
permits updating the entry stored at the Highest-Priority  
Match location. In the Enhanced mode, devices are enabled  
to respond to some command and data writes, as noted in  
Table 5b on page 11, but not command and data reads.  
When the Control register is set to the Enhanced mode,  
you can continue to write data to the Comparand register  
or issue a Move to Next Free Address instruction without  
first having to issue a NOP with /EC HIGH to unlock the  
daisy chain after a Compare cycle with no match, as  
indicated in cases 4 and 5 of Table 5b on page 11. In this  
mode, data write cycles as well as command write cycles  
are enabled in all devices even when /EC is LOW.  
Exceptions are data writes, moves, or VBC instructions  
involving HM, which occur only in the device with the  
highest match; and data writes or move instructions  
involving NF, which occur only in the device with /FI LOW  
and /FF HIGH. The Enhanced mode speeds up system  
performance by eliminating the need to unlock the daisy chain  
before Command or Data Write cycles.  
Table 5a (Standard mode) and Table 5b (Enhanced mode)  
show when a device will respond to reads or writes and  
when it will not, based on the state of /EC(int), the internal  
match condition, and other control inputs. /EC is latched  
by the falling edge of /E. /EC(int) is registered from the  
latched /EC signal off the rising edge of /E, so it controls  
what happens in the next cycle, as shown in Figure 6. When  
/EC is first taken LOW in a string of LANCAM devices  
(and assuming the Device Select registers are set to FFFFH),  
all devices will respond to that command write or data write.  
Full Flag Cascading  
The Full Flag daisy chain cascading is used for three  
purposes: first, to allow instructions that address Next Free  
locations to operate globally; second, to provide a system  
wide Full flag; third, to allow the loading of the Page  
Address registers during initialization using the SFF  
instruction. The full flag logic causes only the device  
containing the first empty location to respond to Next Free  
instructions such as MOV NF,CR,V, which will move the  
contents of the Comparand register to the first empty  
location in a string of devices and set that location Valid,  
so it will be available for the next automatic compare. With  
devices connected as in Figure 1a on page 6, the /FF output  
of the last device in a string provides a full indication for  
the entire string.  
From then on the daisy chain will remain locked in each  
subsequent cycle as long as /EC is held LOW on the falling  
edge of /E in the current cycle. When the daisy chain is  
locked in the Standard mode, only the Highest-Priority  
Match device will respond (See Case 6 of Table 5a on page  
11). If, for example, all of the CAM memory locations were  
empty, there would be no match, and /MF would stay HIGH.  
Since none of the devices could then be the Highest-Priority  
Match device, none will respond to reads or writes until  
the daisy chain is unlocked by taking /EC HIGH and  
asserting /E for a cycle.  
If there is a match between the data in the Comparand  
register and one or more locations in memory, then only the  
Rev. 3a  
14  
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