MU9C4480A/L
OPERATIONAL CHARACTERISTICS Continued
must have a unique Page Address value stored in its PA
register, or contention will result. After all the PA
registers are filled, the entire string is reset through the
Control register, which does not change the values stored
in the individual PA registers. After the reset, the Device
Select registers are usually set to FFFFH to enable
operation in Case 1 of Table 5a on page 11. The Control
registers and the Segment Control registers are then set
to their normal operating values for the application.
IEEE 802.3/802.5 Format Mapping
To support the symmetrical mapping between the address
formats of IEEE 802.3 and IEEE 802.5, the LANCAM
provides a bit translation facility. Formally expressed,
the nth input bit, D(n), maps to the xth output bit, Q(x),
through the following expressions:
D(n) = Q(7–n) for 0 ≤n ≤ 7,
D(n) = Q(23–n) for 8 ≤ n ≤ 15
Vertically Cascaded System Initialization
Table 6 shows an example of code that initializes a daisy-
chained string of LANCAM devices. The initialization
example shows how to set the Page Address registers of
each of the devices in the chain through the use of the
Set Full Flag instruction, and how the Control registers
and Segment counters of all the LANCAM devices are
set for a typical application. Each Page Address register
must contain a unique value (not FFFFH) to prevent bus
contention.
Setting Control Register Bits 10 and 9 selects whether to
persistently translate, or persistently not to translate,
the data written onto the 64-bit internal bus. The default
condition after a Reset command is not to translate the
incoming data. Figure 2 on page 7 shows the bit mapping
between the two formats.
INITIALIZING THE LANCAM
Initialization of the LANCAM is required to configure
the various registers on the device. Since a Control
register reset establishes the operating conditions shown
in Table 4 on page 9, restoration of operating conditions
better suited for the application may be required after a
reset, whether using the Control Register reset, or
the /RESET pin. When the device powers up, the memory
and registers are in an unknown state, so the /RESET pin
must be asserted to place the device in a known state.
For typical daisy chain operation, data are loaded into
the Comparand registers of all the devices in a string
simultaneously by setting DS=FFFFH. Since reading is
prohibited when DS=FFFFH except for the device with a
match, for a diagnostic operation you need to select a
specific device by setting DS=PA for the desired device
to be able to read from it. Refer to Tables 5a and 5b on
page 11 for preconditions for reading and writing.
Initialization for a single LANCAM is similar. The Device
Select register in this case is usually set to equal the
Page Address register for normal operations. Also, the
dedicated /MA flag output can be used instead of /MF,
allowing /EC to be tied HIGH.
Setting Page Address Register Values
In a vertically cascaded system, the user must set the
individual Page Address registers to unique values by
using the Page Address initialization mechanism. Each
Page Address register must contain a unique value to
prevent bus contention. This process allows individual
device selection. The Page Address register initialization
works as follows: Writes to Page Address registers are
only active for devices with /FI LOW and /FF HIGH. At
initialization, all devices are empty, thus the top device
in the string will respond to a TCO PA instruction, and
load its PA register. To advance to the next device in the
string, a Set Full Flag (SFF) instruction is used, which is
also only active for the device with /FI LOW and /FF
HIGH. The SFF instruction changes the first device’s
/FF to LOW, although the device really is empty, which
allows the next device in the string to respond to the
TCO PA instruction and load its PA register. The
initialization proceeds through the chain in a similar
manner filling all the PA registers in turn. Each device
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Rev. 3a
MUSIC [ MUSIC SEMICONDUCTORS ]
