MU9C4480A/L
OPERATIONAL CHARACTERISTICS Continued
Notes
Control Bus
Comments
Op-Code
Cycle Type
on DQ Bus
/E /CM /W /EC
Clear power-up anomalies
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
Command Read
Command Write
Command Write
Command Write
Command Write
Command Write
Command Write
Command Write
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
Target Device Select Register to disable local device section
Disable Device Select feature
TCO DS
FFFFH
TCO CT
0000H
TCO PA
nnnnH
SFF
Target Control register for reset
Causes Reset
1
2
Target Page Address register to set page for cascaded operation
Page Address value
2
Set Full flag; allows access to next device (repeat previous
2 cycles plus this one for each device in chain
Target Control register for reset of Full flags, but not Page address
Causes Reset
2,3
TCO CT
0000H
L
L
L
L
L
L
L
L
L
L
L
L
1
1
4
4
Command Write
Command Write
Command Write
Command Write
Command Write
Command Write
L
L
L
L
L
L
H
H
H
H
H
H
Target Control register for initial values
Control register value
TCO CT
8040H
Target Segment Counter Control register
Set both Segment Counters to write to Segment 1, 2, and 3 and
read from Segment 0
TCO SC
3808H
4
Command Write
L
L
L
H
SPS M@HM
Set Data Reads from Segment 0 of the Highest-priority match
Notes:
1. Toggling the /Reset pin generates the same effect as this reset of the Control register, but good programming
practice dictates a software reset for initialization to account for all possible prior conditions.
2. This instruction may be omitted for a single LANCAM application.
3. The last SFF will cause the /FF pin in the last chip in a daisy chain to go LOW. In a daisy chain, DS needs to be set equal to PA
to read out a particular chip prior to a match condition.
4. A typical LANCAM control environment: Enable match flag; Enable full flag; 48 CAM bits, 16 RAM bits; Disable comparison
masking; and Enable address increment. See Table 8 for Control Register bit assignments.
Table 6: Example Initialization Routine
INSTRUCTION SET DESCRIPTIONS*
Instruction: Select Persistent Source (SPS)
Binary Op-Code: 0000 f000 0000 0sss
vvv
Validity setting for Memory Location
destinations
f
Address Field flag†
Selected source
This instruction selects a persistent destination for data
writes, which remains until another SPD instruction changes
it or a reset occurs. The default destination for Data Write
cycles is the Comparand register after a reset. When the
destination is the Comparand register or the memory array,
the data written may be masked by either Mask Register 1
or Mask Register 2, so that only destination bits
corresponding to bits in the mask register set to 0 will be
modified. An automatic compare will occur after writing the
last segment of the Comparand or mask registers, but
not after writing to memory. Setting the persistent
destination to M@aaaH loads the Address register with
“aaaH,” and the first access to that persistent destination
will be at aaaH, after which the AR value increments or
decrements as set in the Control register. The SPD
M@[AR] instruction does the same except the current
Address Register value is used.
sss
This instruction selects a persistent source for data reads,
until another SPS instruction changes it or a reset occurs.
The default source after reset for Data Read cycles is the
Comparand register. Setting the persistent source to
M@aaaH loads the Address register with “aaaH” and the
first access to that persistent source will be at aaaH, after
which the AR value increments or decrements as set in the
Control register. The SPS M@[AR] instruction does the
same except the current Address Register value is used.
Instruction: Select Persistent Destination (SPD)
Binary Op-Code: 0000 f001 mmdd dvvv
f
mm
ddd
Address Field flag†
Mask Register select
Selected destination
Rev. 3a
16
MUSIC [ MUSIC SEMICONDUCTORS ]
