MU9C4480A/L
INSTRUCTION SET SUMMARY Continued
Instruction: Data Move Continued
Memory at Next Free Address, No Change to Validity bits, from:
Operation
Mnemonic
Op-Code
Comparand Register
Masked byMR1
Masked byMR2
Mask Register 1
Mask Register 2
MOV NF,CR
0330H
0370H
03B0H
0331H
0332H
Mask Register 1 from:
Comparand Register
No Operation
MOV NF,CR[MR1]
MOV NF,CR[MR2]
MOV NF,MR1
MOV MR1,CR
NOP
0308H
0309H
030AH
030CH
0B0CH
030DH
Mask Register 2
Memory at Address Reg.
Memory at Address
MOV MR1,MR2
MOV MR1,[AR]
MOV MR1,aaaH
MOV NF,MR2
Memory at Next Free Address, Location set Valid, from:
Mem. at Highest-Prio. Match MOV MR1,HM
Comparand Register
Masked byMR1
Masked byMR2
Mask Register 1
Mask Register 2
MOV NF,CR,V
0334H
0374H
03B4H
0335H
0336H
MOV NF,CR[MR1],V
MOV NF,CR[MR2],V
MOV NF,MR1,V
MOV NF,MR2,V
Mask Register 2 from:
Comparand Register
Mask Register 1
No Operation
MOV MR2,CR
MOV MR2,MR1
NOP
0310H
0311H
0312H
0314H
0B14H
0315H
Memory at Address Reg.
Memory at Address
MOV MR2,[AR]
MOV MR2,aaaH
Instruction: Validity Bit Control
Operation
Mnemonic
Op-Code
Mem. at Highest-Prio. Match MOV MR2,HM
Set Validity bits at Address Register
Memory at Address Register, No Change to Validity bits, from:
Set Valid
Set Empty
Set Skip
Set Random Access
VBC [AR],V
0424H
0425H
0426H
0427H
Comparand Register
Masked by MR1
Masked byMR2
Mask Register 1
Mask Register 2
MOV [AR],CR
0320H
0360H
03A0H
0321H
0322H
VBC [AR],E
VBC [AR],S
VBC [AR],R
MOV [AR],CR[MR1]
MOV [AR],CR[MR2]
MOV [AR],MR1
MOV [AR],MR2
Set Validity bits at Address
Set Valid
Set Empty
Set Skip
Set Random Access
VBC aaaH,V
VBC aaaH,E
VBC aaaH,S
VBC aaaH,R
0C24H
0C25H
0C26H
0C27H
Memory at Address Register, Location set Valid, from:
Comparand Register
Masked by MR1
Masked byMR2
Mask Register 1
Mask Register 2
MOV [AR],CR,V
0324H
0364H
03A4H
0325H
0326H
MOV [AR],CR[MR1],V
MOV [AR],CR[MR2],V
MOV [AR],MR1,V
MOV [AR],MR2,V
Set Validity bits at Highest-Priority Match
Set Valid
Set Empty
Set Skip
VBC HM,V
VBC HM,E
VBC HM,S
VBC HM,R
042CH
042DH
042EH
042FH
Memory at Address, No Change to Validity bits, from:
Set Random Access
Comparand Register
Masked byMR1
Masked byMR2
Mask Register 1
Mask Register 2
MOV aaaH,CR
0B20H
0B60H
0BA0H
0B21H
0B22H
MOV aaaH,CR[MR1]
MOV aaaH,CR[MR2]
MOV aaaH,MR1
MOV aaaH,MR2
Set Validity bits at All Matching Locations
Set Valid
Set Empty
Set Skip
VBC ALM,V
VBC ALM,E
VBC ALM,S
VBC ALM,R
043CH
043DH
043EH
043FH
Set Random Access
Memory at Address, Location set Valid, from:
Comparand Register
Masked byMR1
Masked byMR2
Mask Register 1
Mask Register 2
MOV aaaH,CR,V
MOV aaaH,CR[MR1],V 0B64H
MOV aaaH,CR[MR2],V 0BA4H
MOV aaaH,MR1,V
MOV aaaH,MR2,V
0B24H
Instruction: Compare
Operation
Mnemonic
CMP V
CMPE
Op-Code
0504H
0B25H Compare Valid Locations
0B26H Compare Empty Locations
Compare Skipped Locations
0505H
0506H
CMPS
Memory at Highest-Priority Match, No Change to Validity bits,
from:
Comp. Random Access Locations CMPR
0507H
Comparand Register
Masked byMR1
Masked byMR2
Mask Register 1
Mask Register 2
MOV HM,CR
0328H
0368H
03A8H
0329H
032AH
Instruction: Special Instructions
MOV HM,CR[MR1]
MOV HM,CR[MR2]
MOV HM,MR1
MOV HM,MR2
Operation
Mnemonic
Op-Code
0600H
Shift Comparand Right
Shift Comparand Left
Shift Mask Register 2 Right
Shift Mask Register 2 Left
SFT CR, R
SFT CR, L
SFT M2, R
SFT M2, L
0601H
0610H
0611H
0618H
0619H
Memory at Highest-Priority Match, Location set Valid, from:
Select Foreground Registers SFR
Select Background Registers SBR
Reset Seg. Cont. Reg. to Initial Val. RSC
Comparand Register
Masked byMR1
Masked byMR2
Mask Register 1
Mask Register 2
MOV HM,CR,V
032CH
036CH
03ACH
032DH
032EH
MOV HM,CR[MR1],V
MOV HM,CR[MR2],V
MOV HM,MR1,V
MOV HM,MR2,V
061AH
Instruction: Miscellaneous Instructions
Operation
No Operation
Set Full Flag
Mnemonic
NOP
SFF
Op-Code
0300H
0700H
19
Rev. 3a
MUSIC [ MUSIC SEMICONDUCTORS ]
