MU9C4480A/L
OPERATIONAL CHARACTERISTICS Continued
/EC needs to be LOW at the start of the cycle prior to any
VERTICAL CASCADING
cycle that requires a locked daisy chain, such as a Status
register or associated data read after a match. If there is no
match in Standard mode, the output buffers stay Hi-Z, and
the daisy chain must be unlocked by taking /EC HIGH
during a NOP or other non-functioning cycle, as indicated
in Table 5a on page 11. Figure 6 shows how the internal /EC
timing holds the daisy chain locking effect over into the
next cycle. In the Enhanced mode, this NOP is not needed
before data or command writes following a non-matching
compare, as indicated by Table 5b on page 11. A single-
chip system does not require daisy-chained match flag
operation, hence /EC could be tied HIGH and the /MA pin
or flag in the Status register used instead of /MF, allowing
access to the device regardless of the match condition.
LANCAMs can be vertically cascaded to increase system
depth. Through the use of flag daisy-chaining, multiple
devices will respond as an integrated system. The flag
daisy chain allows all commands to be issued globally,
with a response only in the device containing the Highest-
Priority Matching or Next Free location. When connected
in a daisy chain, the last device’s Full flag and Match flag
accurately report the condition for the whole string. A
system in which LANCAMs are vertically cascaded using
daisy-chaining of the flags is shown in Figure 1a on page 6.
To operate the daisy chain, the Device Select registers are
set to FFFFH to enable all devices to execute Command
Write and Data Write cycles. In normal operation, read
cycles are enabled from the device with the highest-priority
match by locking the daisy chain (see the “Locked Daisy
Chain” section). An individual device in the chain may be
targeted for a read or write operation by temporarily setting
the Device Select registers to the Page address of the target
device. Setting the Device Select registers back to FFFFH
restores the operation of the entire daisy chain.
The minimum timings for the /E control signal are given in
the Switching Characteristics section on page 24. Note that
at minimum timings the /E signal is non-symmetrical, and
that different cycle types have different timing requirements,
as given in Table 7 on page 20.
COMPARE OPERATIONS
Match Flag Cascading
During a Compare operation, the data in the Comparand
register is compared to all locations in the Memory array
simultaneously. Any mask register used during compares
must be selected beforehand in the Control register. There
are two ways compares are initiated: Automatic and Forced
compares.
The Match Flag daisy chain cascading is used for three
purposes: first, to allow operations on Highest-Priority
Match addresses to be issued globally over the whole
string; second, to provide a system wide match flag; third,
to lock out all devices except the one with the Highest-
Priority match for instructions such as Status reads after a
match. The Match flag logic causes only the highest-
priority device to operate on its Highest-Priority Match
location while devices with lower-priority matches ignore
Highest-Priority Match operations. The lock-out feature is
enabled by the match flag cascading and the use of the /EC
control signal, as shown in Tables 5a and 5b on page 11.
Automatic compares perform a compare of the contents of the
Comparand register against Memory locations that are tagged
as “Valid,” and occur whenever the following happens:
Ø The Destination Segment counter in the Segment
Control register reaches its end limit during writes to
the Comparand or mask registers.
/E
Ø After a command write of a TCO CT is executed (except
for a software reset), so that a compare is executed
with the new settings of the Control register.
/EC
Forced compares are initiated by CMP instructions
using one of the four validity conditions, V, R, S, and E.
The forced compare against “Empty” locations
automatically masks all 64 bits of data to find all locations
with the validity bits set to “Empty,” while the other
forced compares are only masked as selected in the
Control register.
/EC (INT)
/MF
Figure 6: /EC(int) Timing Diagram
Rev. 3a
13
MUSIC [ MUSIC SEMICONDUCTORS ]
