MU9C4480A/L
INSTRUCTION SET SUMMARY Continued
CYCLETYPE
Command Read
CYCLE
LENGTH
Data Write
Command Write
Data Read
Comparand register
(not last segment)
Mask register
MOV reg, reg (except L-70)
TCO reg (except CT)
TCO CT (non-reset, HMA invalid)
SPS, SPD, SFR
Short
(not last segment)
SBR, RSC
NOP (except L-70)
SFT (A)
MOV reg, reg (L-70)
Medium
Memory array
(NFA invalid)
Status register or
16-bit register
Comparand register
Mask register
MOV reg, mem
TCO CT (reset)
VBC (NFA invalid)
NOP (L-70)
SFT (L)
Long
MOV mem, reg
TCO CT (non-reset, HMA valid)
CMP
SFF
Memory array
(NFA valid)
Comparand register
(last segment)
Mask register
(last segment)
Memory array
VBC (NFA valid)
Note: The specific timing requirements for Short, Medium, and Long cycles are given in the Switching Characteristics
Section under the tELEH parameter. For two cycle Command Writes (TCO reg or any instruction with “aaaH” as
the source or destination), the first cycle is short, and the second cycle will be the length given.
Table 7: Instruction Cycle Lengths
REGISTER BIT ASSIGNMENTS
15
14
13 12
11 10
9
8
7
6
5
4
3
2
1
0
RST Match Flag Full Flag Translation
CAM/RAM Part.
Comp. Mask AR Inc/Dec
Mode
64 CAM/0 RAM = 000
48 CAM/16 RAM = 001
32 CAM/32 RAM = 010
16 CAM/48 RAM = 011
48 RAM/16 CAM = 100
32 RAM/32 CAM = 101
16 RAM/48 CAM = 110
No Change = 111
None = 00
MR1 = 01
MR2 = 10
No Change
= 11
Increment
= 00
Decrement
= 01
Disable
= 10
No Change
= 11
Standard
Mode
= 00
Enhanced
Mode
= 01
Reserved
= 10
No Change
= 11
R
E
S
E
T
=
0
Enable
=00
Disable
= 01
No Change
= 11
Enable
= 00
Disable
= 01
Input Not
Translated
= 00
Input
No Change Translated
= 11
= 01
No Change
= 11
Note: D15 reads back as 0.
Table 8: Control Register Bit Assignments
Rev. 3a
20
MUSIC [ MUSIC SEMICONDUCTORS ]
