MU9C4480A/L
REGISTER BIT ASSIGNMENTS Continued
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DCSL
SSL
SCSL
LSC
SSCV
SDL
DCEL
LDC
DSCV
SCEL
Set
Dest.
Seg.
Limits
= 0
Set
Source
Seg.
Limits
= 0
Load
Dest.
Seg.
Count
= 0
Load
Src.
Seg.
Count
= 0
Destination
Count
End
Limit
=00–11
Source
Count
Start
Limit
=00–11
Source
Count
End
Limit
=00–11
Destination
Seg.
Count
Value
=00–11
Source
Seg.
Count
Value
Destination
Count
Start
Limit
=00–11
=00–11
No
No
No
No
Chng.
= 1
Chng.
= 1
Chng.
= 1
Chng.
= 1
Note: D15, D10, D5, and D2 read back as 0s.
Table 9: Segment Control Register Bit Assignments
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Page Address, PA3–0
Next Free Address, NF11–0
Note: The Next Free Address register is read only, and is accessed by performing a Command Read
cycle immediately following a TCO NF instruction.
Table 10: Next Free Address Register Bit Assignments
31
30
29
28
27
11
26
10
25
9
24
23
22
21
20
19
3
18
2
17
1
16
/MM Skip Empty
/FL
Page Address Bits, PA 14–3
15
14
13
12
8
7
6
5
4
0
Match Address, AM11-0
PA2–0
/MA
Note: The Status register is read only, and is accessed by performing Command Read cycles.
On the first cycle, bits 15–0 will be output, and if a second Command Read cycle is issued
immediately after the first Command Read cycle, bits 31–16 will be output.
Table 11: Status Register Bit Assignments
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Device ID = 440H
PS
Note: The Persistent Source register is read only, and is accessed by performing a Command Read
cycle immediately following a TCO PS instruction.
Table 12: Persistent Source Register Bit Assignments
21
Rev. 3a
MUSIC [ MUSIC SEMICONDUCTORS ]
