MU9C4480A/L
INSTRUCTION SET SUMMARY
MNEMONIC FORMAT
INS dst,src[msk],val
Instruction: Select Persistent Destination Cont.
Operation
Mnemonic
Op-Code
012DH
Mem. at Highest-Prio. Match, Emp. SPDM@HM,E
INS: Instruction mnemonic
dst: Destination of the data
Masked by MR1
Masked by MR2
SPDM@HM[MR1],E
SPD M@HM[MR2],E
016DH
01ADH
src: Source of the data
msk: Mask register used
val: Validity condition set at the location written
Mem. at Highest-Prio. Match, Skip SPDM@HM,S
012EH
016EH
01AEH
Masked by MR1
Masked by MR2
SPD M@HM[MR1],S
SPDM@HM[MR2],S
Mem. at High.-Prio. Match, Random SPD M@HM,R
012FH
016FH
01AFH
Instruction: Select Persistent Source
Masked by MR1
Masked by MR2
SPD M@HM[MR1],R
SPD M@HM[MR2],R
Operation
Comparand Register
Mask Register 1
Mnemonic
SPS CR
SPS MR1
Op-Code
0000H
0001H
0002H
0004H
0804H
Mem. at Next Free Addr., Valid SPD M@NF,V
0134H
0174H
01B4H
Mask Register 2
SPS MR2
Masked by MR1
Masked by MR2
SPD M@NF[MR1],V
SPD M@NF[MR2],V
Memory Array at Addr. Reg.
Memory Array at Address
Mem. at Highest-Prio. Match
SPS M@[AR]
SPS M@aaaH
SPSM@HM
0005H
Mem. at Next Free Addr., Empty SPD M@NF,E
0135H
0175H
01B5H
Masked by MR1
Masked by MR2
SPD M@NF[MR1],E
SPD M@NF[MR2],E
Instruction: Select Persistent Destination
Operation
Mnemonic
SPD CR
SPD CR[MR1]
SPD CR[MR2]
Op-Code
0100H
Mem. at Next Free Addr., Skip SPD M@NF,S
0136H
0176H
01B6H
Masked by MR1
Masked by MR2
SPD M@NF[MR1],S
SPD M@NF[MR2],S
Comparand Register
Masked by MR1
Masked by MR2
0140H
0180H
Mem. at Next Free Addr., Random SPD M@NF,R
0137H
0177H
01B7H
Mask Register 1
Mask Register 2
Mem. at Addr. Reg. set Valid
Masked by MR1
SPD MR1
SPD MR2
SPD M@[AR],V
SPD M@[AR][MR1],V
SPD M@[AR][MR2],V
0108H
0110H
0124H
0164H
01A4H
Masked by MR1
Masked by MR2
SPD M@NF[MR1],R
SPD M@NF[MR2],R
Instruction: Temporary Command Override
Masked by MR2
Operation
Mnemonic
TCO CT
TCO PA
TCO SC
TCO NF
TCO AR
TCO DS
TCO PS
TCO PD
Op-Code
0200H
0208H
0210H
0218H
0220H
0228H
0230H
0238H
Control Register
Mem. at Addr. Reg. set Empty SPD M@[AR],E
0125H
0165H
01A5H
Page Address Register
Segment Control Register
Read Next Free Address
Address Register
Device Select Register
Read Persistent Source
Read Persistent Destination
Masked by MR1
Masked by MR2
SPDM@[AR][MR1],E
SPDM@[AR][MR2],E
Mem. at Addr. Reg. set Skip
Masked by MR1
SPD M@[AR],S
SPD M@[AR][MR1],S
SPD M@[AR][MR2],S
0126H
0166H
01A6H
Masked by MR2
Mem. at Addr. Reg. set Random SPD M@[AR],R
0127H
0167H
01A7H Operation
Instruction: Data Move
Masked by MR1
Masked by MR2
SPD M@[AR][MR1],R
SPD M@[AR][MR2],R
Mnemonic
Op-Code
Comparand Register from:
No Operation
Mask Register 1
Mask Register 2
Memory at Address Reg.
Masked by MR1
Memory at Address set Valid SPD M@aaaH,V
Masked by MR1
0924H
0964H
09A4H
NOP
0300H
0301H
0302H
0304H
0344H
0384H
SPD M@aaaH[MR1],V
MOV CR,MR1
MOV CR,MR2
MOV CR,[AR]
MOV CR,[AR][MR1]
MOV CR,[AR][MR2]
Masked by MR2
SPD M@aaaH[MR2],V
Memory at Addr. set Empty
Masked by MR1
SPD M@aaaH,E
SPD M@aaaH[MR1],E
SPD M@aaaH[MR2],E
0925H
0965H
09A5H
Masked by MR2
Masked by MR2
Memory at Address
Masked by MR1
Masked by MR2
MOV CR,aaaH
MOV CR,aaaH[MR1]
MOV CR,aaaH[MR2]
0B04H
0B44H
0B84H
Memory at Address set Skip
Masked by MR1
SPD M@aaaH,S
SPD M@aaaH[MR1],S
SPD M@aaaH[MR2],S
0926H
0966H
09A6H
Masked by MR2
Mem. at Address set Random SPD M@aaaH,R
0927H
0967H
09A7H
Mem. at Highest-Prio. Match MOV CR,HM
0305H
0345H
0385H
Masked by MR1
Masked by MR2
SPD M@aaaH[MR1],R
SPD M@aaaH[MR2],R
Masked by MR1
Masked by MR2
MOV CR,HM[MR1]
MOV CR,HM[MR2]
Mem. at Highest-Prio. Match, Valid SPD M@HM,V
012CH
016CH
01ACH
Masked by MR1
Masked by MR2
SPD M@HM[MR1],V
SPD M@HM[MR2],V
Rev. 3a
18
MUSIC [ MUSIC SEMICONDUCTORS ]
