V58C2128(804/404/164)S
Precharge Timing During Write Operation
Precharge timing for Write operations in DRAMs requires enough time to satisfy the write recovery require-
ment. This is the time required by a DRAM sense amp to fully store the voltage level. For DDR SDRAMs, a
timing parameter (tWR) is used to indicate the required amount of time between the last valid write operation
and a Precharge command to the same bank.
The “write recovery” operation begins on the rising clock edge after the last DQS edge that is used to strobe
in the last valid write data. “Write recovery” is complete on the 2nd next rising clock edge that is used to strobe
in the Precharge command.
Write with Precharge Timing
(CAS Latency = Any; Burst Length = 4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
tRAS(min)
t
RP(min)
CK, CK
BA
NOP
NOP
Write
NOP
NOP
NOP
PreA
NOP
BA
NOP
tWR
Command
DQS
DQ
D0
D1 D2 D3
tWR
DQS
DQ
D0
D1 D2 D3
V58C2128(804/404/164)S Rev. 1.6 March 2002
20
MOSEL [ MOSEL VITELIC, CORP ]
