V58C2128(804/404/164)S
Burst Stop Command
The Burst Stop command is valid only during burst read cycles and is initiated by having RAS and CAS
high with CS and WE low at the rising edge of the clock. When the Burst Stop command is issued during a
burst Read cycle, both the output data (DQ) and data strobe (DQS) go to a high impedance state after a delay
(LBST) equal to the CAS latency programmed into the device. If the Burst Stop command is issued during a
burst Write cycle, the command will be treated as a NOP command.
Read Terminated by Burst Stop Command Timing
(CAS Latency = 2, 2.5, 3; Burst Length = 4)
T0
T1
T2
T3
T4
T5
T6
CK, CK
Read
BST
NOP
NOP
NOP
NOP
Command
L
BST
DQS
DQ
CAS Latency = 2
D
D
1
0
L
L
BST
BST
DQS
DQ
CAS Latency = 2.5
D
D
1
0
V58C2128(804/404/164)S Rev. 1.6 March 2002
16
MOSEL [ MOSEL VITELIC, CORP ]
