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V58C2128804S 参数 Datasheet PDF下载

V58C2128804S图片预览
型号: V58C2128804S
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能2.5伏128兆位的DDR SDRAM [HIGH PERFORMANCE 2.5 VOLT 128 Mbit DDR SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 59 页 / 922 K
品牌: MOSEL [ MOSEL VITELIC, CORP ]
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V58C2128(804/404/164)S  
Read Interrupted by a Write  
To interrupt a Burst Read with a Write command, a Burst Stop command must be asserted to stop the burst  
read operation and 3-state the DQ bus. Additionally, control of the DQS bus must be turned around to allow  
the memory controller to drive the data strobe signal (DQS) into the DDR SDRAM for the write cycles. Once  
the Burst Stop command has been issued, a Write command can not be issued until a minimum delay or  
latency (LBST) has been satisfied. This latency is measured from the Burst Stop command and is equivalent  
to the CAS latency programmed into the mode register. In instances where CAS latency is measured in half  
clock cycles, the minimum delay (LBST) is rounded up to the next full clock cycle (i.e., if CL=2 then LBST=2, if  
CL=2.5 then LBST=3). It is illegal to interrupt a Read with autoprecharge command with a Write command.  
Read Interrupted by Burst Stop Command Followed by a Write Command Timing  
(CAS Latency = 2; Burst Length = 4)  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
T9  
CK, CK  
Command  
DQS  
Read  
BST  
NOP  
Write  
NOP  
NOP  
NOP  
NOP  
D0  
D1  
D0 D1 D2 D3  
DQ  
LBST  
Write Interrupted by a Write  
A Burst Write can be interrupted before completion by a new Write command to any bank. When the pre-  
vious burst is interrupted, the remaining addresses are overridden with a full burst length starting with the new  
address. The data from the first Write command continues to be input into the device until the Write Latency  
of the interrupting Write command is satisfied (WL=1) At this point, the data from the interrupting Write com-  
mand is input into the device. Write commands can be issued on each rising edge of the system clock. It is  
illegal to interrupt a Write with autoprecharge command with a Write command.  
Write Interrupted by a Write Command Timing  
(CAS Latency = Any; Burst Length = 4)  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
T9  
CK, CK  
Command  
DQS  
Write  
Write  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
A
B
DA0 DA1 DB0 DB1 DB2 DB3  
DM0 DM1 DM0 DM1 DM2 DM3  
DQ  
DM  
Write Latency  
V58C2128(804/404/164)S Rev. 1.6 March 2002  
22  
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