V58C2128(804/404/164)S
Burst Write Timing
(CAS Latency = Any; Burst Length = 4)
T4
T0
T1
T2
T3
CK, CK
WRITE
NOP
NOP
NOP
Command
tWPREH
tWPST
tWPRES
tQDQSS
tDQSS
DQS(nom)
DQ(nom)
tQDQSH
tQDQSS
tQDQSH
D0
D1
D2
D3
tWPREH(min)
tWPRES(min)
DQS(min)
DQ(min)
tDQSS(min)
D0
D1
D2
D3
tWPRES(max)
t
WPREH(max)
DQS(max)
DQ(max)
t
DQSS(max)
D0
D1
D2
D3
Once the burst of write data is concluded and given that no subsequent burst write operations are initiated,
the data strobe signal (DQS) transitions from a logic low level back to Hi-Z. This is referred to as the data
strobe “write postamble”. This transition happens nominally one-half clock period after the last data of the
burst cycle is latched into the device.
V58C2128(804/404/164)S Rev. 1.6 March 2002
18
MOSEL [ MOSEL VITELIC, CORP ]
