V58C2128(804/404/164)S
Write Interrupted by a Precharge
A Burst Write can be interrupted before completion of the burst by a Precharge command, with the only
restriction being that the interval that separates the commands be at least one clock cycle.
Write Interrupted by a Precharge Timing
(CAS Latency = 2; Burst Length = 8)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CK, CK
Command
DQS
Write
Pre
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
A
A
t
WR
D
D
D
D
D
D
D
6
DQ
0
1
2
3
4
5
DM
Data is masked
by DM input
Data is masked
by Precharge Command
DQS input ignored
Write with Auto Precharge
If A is high when a Write command is issued, the Write with auto Precharge function is performed. Any
10
new command to the same bank should not be issued until the internal precharge is completed. The internal
precharge begins after keeping t
(min.).
WR
Write with Auto Precharge Timing
(CAS Latency = Any; Burst Length = 4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
tRAS(min)
CK, CK
BA
NOP
NOP
WAP
NOP
NOP
NOP
NOP
NOP
NOP
BA
Command
DQS
DQ
tWR(min)
tRP(min)
D0
D1 D2 D3
Begin Autoprecharge
V58C2128(804/404/164)S Rev. 1.6 March 2002
19