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V58C2128804S 参数 Datasheet PDF下载

V58C2128804S图片预览
型号: V58C2128804S
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能2.5伏128兆位的DDR SDRAM [HIGH PERFORMANCE 2.5 VOLT 128 Mbit DDR SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 59 页 / 922 K
品牌: MOSEL [ MOSEL VITELIC, CORP ]
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V58C2128(804/404/164)S  
Precharge Timing During Read Operation  
For the earliest possible Precharge command without interrupting a Read burst, the Precharge command  
may be issued on the rising clock edge which is CAS latency (CL) clock cycles before the end of the Read  
burst. A new Bank Activate (BA) command may be issued to the same bank after the RAS precharge time  
(tRP). A Precharge command can not be issued until tRAS(min) is satisfied.  
Read with Precharge Timing as a Function of CAS Latency  
(CAS Latency = 2, 2.5, 3; Burst Length = 4)  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
T9  
tRAS(min)  
tRP(min)  
CK, CK  
BA  
NOP  
NOP  
Read  
NOP  
PreA  
NOP  
BA  
NOP  
NOP  
Command  
DQS  
DQ  
D0  
D1 D2 D3  
CAS Latency=2  
DQS  
DQ  
D0  
D1 D2 D3  
CAS Latency=2.5  
V58C2128(804/404/164)S Rev. 1.6 March 2002  
15  
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