MT9092
Quiet Code
The DSP can be made to send quiet code to the
decoder and receive filter path by setting the
RxMUTE bit high. Likewise, the DSP will send quiet
code in the transmit (DSTo) path when the TxMUTE
bit is high. Both of these control bits reside in the
DSP Control Register at address 1Eh. When either
of these bits are low, their respective paths function
normally.
HDLC
The High-level Data Link Control (HDLC) block is
located, functionally, between the serial ST-BUS port
and the serial Microcontroller port. This functional
block handles the bit oriented protocol requirements
of layer 2 X.25 packet switching and Q.921 link
access protocols defined by CCITT. The HDLC is
dedicated to D-Channel operation at 16kb/s and
offers buffered access to the serial D-Channel data
through separate 19 byte transmit and receive
FIFOs.
The HDLC generates and detects the flags, various
link channel states and abort sequences as well as
performing a cyclic redundancy check on data
packets according to the CCITT defined polynomial.
Lastly, the protocol functions may be disabled to
provide transparent access, of the serial port D-
Channel, to the microport.
A power up reset (PWRST, pin 6) or a software reset
via RST (address 0Fh) will cause the HDLC
transceiver to be initialized. This results in the
transmitter and receiver being disabled and all HDLC
registers defaulting to their power reset values.
HDLC Frame Structure
A valid HDLC frame begins with an opening flag,
contains at least 16 bits of address, control or
information, ends with a 16 bit FCS followed by a
closing flag. Data formatted in this manner is also
referred to as a "packet". Refer to Figure 4.
FLAG
One
Byte
DATA FIELD
n Bytes
(n≥2)
FCS
Two
Bytes
FLAG
One
Byte
generates flags and appends them to the packet to
be transmitted. The receiver searches the incoming
data stream for flags on a bit-by-bit basis to establish
frame synchronization. The receiver uses flags for
synchronization only and does not transfer them to
the Rx FIFO.
Address Field
The address field consists of one or two 8-bit bytes
directly following the opening flag. Address, Control
and Information fields are known collectively as the
Data field.
Control Field
The control field consists of one 8-bit byte directly
following the address field. The HDLC does not
distinguish between the control field and the
information field.
Information Field
The information field immediately follows the control
field and consists of N bytes of data where one byte
contains 8 bits. A packet does not need to contain an
information field to be valid. The HDLC does not
distinguish between the control field and the
information field.
Frame Checking Sequence Field
The 16 bits preceding a closing flag are the FCS
field. A cyclic redundancy check utilizing the CRC-
CCITT standard generator polynomial X
16
+ X
12
+X
5
+1 produces the 16-bit FCS. In the transmitter the
FCS is calculated on all bits of the address, control
and information fields. The complement of the FCS
is transmitted, most significant bit first, in the FCS
field. The receiver calculates the FCS on the
incoming packet's address, control, information and
FCS fields and compares the result to 'F0B8'. This
result verifies no transmission errors occurred. If the
packet, between flags, is also at least 32 bits in
length then the address, control and information field
data are entered into the receive FIFO minus the
FCS which is discarded.
Order of Bit Transmission
Address, control and information field data are
entered into the transmit FIFO. This data is then
transmitted and received on the serial bus least
significant bit first. The FCS is sent most significant
bit first on the serial bus. Note that it is the
complement of the calculated FCS which is
transmitted. The HDLC does not distinguish
ADDRESS/CONTROL/INFORMATION bytes except
7-11
Figure 4 - Frame Format
Flag Sequence
All HDLC frames start and end with a unique
sequence of 8 bits. This sequence is 0111 1110
(7Eh). The closing flag of one frame can be the
opening flag of the next frame. The transmitter
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