MT9092
to determine if the packet is of minimum valid length.
These fields are transferred transparently through
the FIFO's.
transmitted packet. If this happens, then the last data
written to the receive FIFO will not correspond
exactly with the last byte received before the frame
abort.
Data Transparency (Zero insertion/deletion)
Interframe Time Fill and Link Channel States
Transparency ensures that the contents of a data
packet do not imitate a flag, go-ahead, frame abort
or idle channel. The contents of a transmitted frame,
between the flags, is examined on a bit-by-bit basis
and a 0 bit is inserted after all sequences of five
contiguous 1 bits (including the last five bits of the
FCS). Upon receiving five contiguous 1s within a
frame the receiver deletes the following 0 bit.
When the HDLC transmitter is not sending packets it
will wait in one of two states.
Interframe Time Fill: This is a continuous series of
flags
occurring
between
frames indicating that the
channel is active but that no
data is being sent.
Invalid Frames
Idle:
An idle channel occurs when at least fifteen
contiguous 1s are transmitted or received.
A frame is invalid if one of the following four
conditions exists. Inserted zeros are not part of a
valid bit count:
In both cases the transmitter will exit the wait state
when data is loaded into the transmit FIFO.
1. If the FCS pattern generated from the received
data does not match the 'F0B8' pattern then the
last data byte of the packet is written to the
receive FIFO with a 'bad packet' indication.
Go-Ahead
A go-ahead is defined as the pattern ‘011111110’
(contiguous 7F’s) and is the occurrence of a frame
abort sequence followed by a zero, outside of the
boundaries of a normal packet. Being able to
2. A short frame exists if there are less than 25 bits
between the flags. Short frames are ignored by
the receiver and nothing is written into the
receive FIFO.
distinguish
a
proper (in packet) frame abort
sequence from one occurring outside of a packet
allows a higher level of signalling protocol which is
not part of the HDLC specifications.
3. Packets which are at least 25 bits in length but
less than 32 bits (between the flags) are also
invalid. In this case the data is written to the
FIFO but the last byte is tagged with a 'bad
packet' indication.
Transmitter
Following initialization and enabling, via the HTxEN
bit (address 03h), the transmitter is in the Idle
Channel State (Mark Idle). Interframe time fill may
be selected by setting the Mark Idle bit (address 03h)
high. The transmitter remains in its programmed
state until data is written to the Tx FIFO. The
transmitter will then proceed as follows:
4. If a frame abort sequence is detected the packet
is invalid. Some or all of the current packet will
reside in the receive FIFO, assuming the packet
length before the abort sequence was at least 26
bits long.
Frame Abort
1)
If the transmitter is in the idle state the present
byte of ones will be completely transmitted
before the opening flag and packet data is
sent.
The transmitter will abort a current packet by
substituting a zero followed by seven contiguous 1s
in place of the normal data. The receiver will abort
upon reception of seven contiguous 1s occurring
between the flags of a packet which contains at least
26 bits.
2)
If the transmitter is in the interframe time fill
state the flag currently being transmitted will be
used as the opening flag followed by the
packet data.
Note that should the last receive byte before the
frame abort end with contiguous 1s, these are
included in the seven 1s required for a receiver
abort. This means that the location of the abort
sequence in the receiver may occur before the
location of the abort sequence in the originally
To assist in loading multiple packets into the transmit
FIFO the last packet byte is tagged with either EOP
(to indicate the end of the current packet) or FA.
Control Register 1 (address 03h) bits EOP (end of
7-12
MITEL [ MITEL NETWORKS CORPORATION ]
