MT90826 CMOS
Advanced Information
Measurement Result from
Frame Delay Bits
Corresponding Input Offset Bits
Input Stream
Offset
FD9
1
FD2
0
FD1
0
FD0
0
IFn3
0
IFn2
0
IFn1
0
IFn0
0
No internal master clock shift
(Default)
+ 1/4 internal master clock shift
+ 1/2 internal master clock shift
+ 3/4 internal master clock shift
+ 1.00 internal master clock shift
+ 1.25 internal master clock shift
+ 1.50 internal master clock shift
+ 1.75 internal master clock shift
+ 2.00 internal master clock shift
+ 2.25 internal master clock shift
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
Table 9 - Frame delay Bits (FD9, FD2-0) and Input Offset Bits (IFn3-0)
F0i
CLK
(16.384MHz)
Internal
master clock
at 32MHz
IFn=0000
IFn=0100
8Mb/s STi Stream
8Mb/s STi Stream
Bit 7
Bit 7
F0i
CLK
(16.384MHz)
Internal
master clock
at 32MHz
IFn=0000
IFn=0100
16Mb/s STi Stream
Bit 7
Bit 7
16Mb/s STi Stream
denotes the 3/4 point of the bit cell
Figure 4 - Examples for Input Offset Delay Timing
16
MITEL [ MITEL NETWORKS CORPORATION ]
