Advanced Information
CMOS MT90826
Read/Write Address:
02 for DOS0 register,
03 for DOS1 register,
H
H
04 for DOS2 register,
05 for DOS3 register,
H
H
06 for DOS4 register,
07 for DOS5 register,
H
H
08 for DOS6 register,
09 for DOS7 register,
H
H
Reset value:
0000 for all DOS registers.
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IF33
IF32
IF31
IF30
IF22
IF21
IF20
IF12
IF11
IF10
IF02
IF01
IF00
IF23
IF13
IF03
DOS0 register
IF63
IF53
IF43
IF83
IF73
IF113
IF153
IF193
IF233
IF72
IF71
IF70
IF62
IF61
IF60
IF52
IF92
IF51
IF91
IF50
IF90
IF42
IF82
IF41
IF81
IF40
IF80
DOS1 register
IF112 IF111 IF110
IF152 IF151 IF150
IF192 IF191 IF190
IF103
IF143
IF183
IF102 IF101 IF100
IF93
DOS2 register
IF142 IF141 IF140 IF133
IF132 IF131 IF130 IF123
IF122 IF121 IF120
DOS3 register
IF173
IF163
IF182 IF181 IF180
IF172 IF171 IF170
IF162
IF202
IF161 IF160
DOS4 register
IF232
IF231
IF230 IF223
IF222
IF221
IF220 IF213
IF212
IF211
IF210 IF203
IF201
IF200
DOS5 register
IF272
IF312
IF271
IF311
IF270
IF262
IF302
IF261
IF301
IF260
IF252
IF292
IF251
IF291
IF250
IF242
IF282
IF241
IF281
IF240
IF280
IF273
IF313
IF263
IF253
IF243
DOS6 register
IF310 IF303
IF300 IF293
IF290 IF283
DOS7 register
Name
(Note 1)
Description
IFn3-0
Input Offset Bits 3,2,1 & 0. These four bits define how long the serial interface receiver
takes to recognize and store bit 0 from the STi pin: i.e., to start a new frame. The input
frame offset can be selected to +2.25 clock periods from the point where the external
frame pulse input signal is applied to the F0i inputs of the device. See Table 9.
When the STi pin has a stream rate of 2.048Mb/s, the input offset can not be adjusted
and the input offset bits have to be set to zero.
Note 1: n denotes a STi stream number from 0 to 31.
Table 8 - Frame Delay Offset Register (DOS) Bits
15
MITEL [ MITEL NETWORKS CORPORATION ]
