MT90826 CMOS
Advanced Information
Frame Boundary
F0i
CLK
(16.384MHz)
Internal
master clock
at 32MHz
Offset Value
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
FEi Input
(FD[8:0] = 06 , frame offset of six C32i clock cycles)
H
(FD9 = 0, sample at internal C32i low phase)
For 8Mb/s, 16Mb/s, 4&8Mb/s and 16&8Mb/s modes
F0i
CLK
(16.384MHz)
Internal
master clock
at 16 MHz
Offset Value
0
1
2
3
4
5
6
7
8
FEi Input
(FD[8:0] = 03 , frame offset of three C16i clock cycles)
H
(FD9 = 0, sample at internal C16i low phase)
For 4Mb/s and 2&4Mb/s modes
F0i
CLK
(16.384MHz)
Internal
master clock
at 8MHz
Offset Value
0
1
2
3
4
FEi Input
(FD[8:0] = 02 , frame offset of two C8i clock cycles)
H
(FD9 = 1, sample at internal C8i high phase)
For 2Mb/s mode
Figure 4 - Example for Frame Alignment Measurement
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