ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V VDD, HSTL, QDRIIb2 SRAM
Figure 4
Bus Cycle State Diagram
RD
RD
LOAD NEW
/RD
READ DOUBLE
READ PORT NOP
R_Init=0
READ ADDRESS
always
Supply voltage
provided
/RD
POWER-UP
WT
Supply voltage
provided
WT
LOAD NEW
WRITE ADDRESS
AT K#↑
/WT
WRITE PORT NOP
WRITE DOUBLE
AT K#↑
always
/WT
NOTE:
1. The address is concatenated with one additional internal LSB to facilitate burst operation. The address order is always fixed as xxx .
. . xxx + 0, xxx . . . xxx + 1. Bus cycle is terminated at the end of this sequence (burst count = 2).
2. State transitions: RD = (R# = LOW); WT = (W# = LOW).
3. Read and write state machines can be simultaneously active.
4. State machine control timing sequence is controlled by K.
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
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