ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V VDD, HSTL, QDRIIb2 SRAM
FBGA BALL DESCRIPTIONS (continued)
SYMBOL
TYPE
DESCRIPTION
Q_
Output
Synchronous Data Outputs: Output data is synchronized to the respective C and C# or to K
and K# rising edges if C and C# are tied HIGH. This bus operates in response to R# commands.
See Ball Assignment figures for ball site location of individual signals. The x8 device uses D0-
D7. The x9 device uses D0-D8. The x18 device uses Q0–Q17. Remaining signals are NC. The x36
device uses Q0–Q35. Remaining signals are NC.
VDD
Supply
Supply
Power Supply: 1.8V nominal. See DC Electrical Characteristics and Operating Conditions for
range.
VDDQ
Power Supply: Isolated Output Buffer Supply. Nominally 1.5V. 1.8V is also permissible. See DC
Electrical Characteristics and Operating Conditions for range.
VSS
NC
Supply
–
Power Supply: GND.
No Connect: These signals are not internally connected and may be connected to ground to
improve package heat dissipation.
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
10
©2002, Micron Technology Inc.
MICRON [ MICRON TECHNOLOGY ]
