64Mb : x4, x8, x16
SDRAM
Fig u re 8
Ra n d o m READ Acce sse s
T0
T1
T2
T3
T4
T5
CLK
COMMAND
ADDRESS
DQ
READ
READ
READ
READ
NOP
NOP
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DOUT
D
OUT
D
OUT
DOUT
n
a
x
m
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
CLK
READ
READ
READ
READ
NOP
NOP
NOP
COMMAND
ADDRESS
DQ
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
D
OUT
D
OUT
D
OUT
D
OUT
n
a
x
m
CAS Latency = 3
TRANSITIONING DATA
NOTE: Each READ command may be to any bank. DQM is LOW.
DON’T CARE
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
©2003, Micron Technology, Inc.
17
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