64Mb : x4, x8, x16
SDRAM
AUTO REFRESH
SDRAM retain s d ata with ou t extern al clockin g.
The SELF REFRESH com m and is initiated like an AUTO
REFRESH com m and except CKE is disabled (LOW).
Once the SELF REFRESH com m and is registered, all
the inputs to the SDRAM becom e “Don’t Care,” with
the exception of CKE, which m ust rem ain LOW.
Once self refresh m ode is engaged, the SDRAM pro-
vides its own internal clocking, causing it to perform its
own AUTO REFRESH cycles. The SDRAM m ust rem ain
in self refresh m ode for a m inim um period equal to
tRAS and m ay rem ain in self refresh m ode for an indefi-
nite period beyond that.
The procedure for exiting self refresh requires a se-
quence of com m ands. First, CLK m ust be stable (stable
clock is defined as a signal cycling within tim ing con-
straints specified for the clock pin) prior to CKE going
back HIGH. Once CKE is HIGH, the SDRAM m ust have
NOP com m ands issued (a m inim um of two clocks) for
tXSR, because tim e is required for the com pletion of
any internal refresh in progress.
AUTO REFRESH is used during norm al operation of
the SDRAM and is analagous to CAS#-BEFORE-RAS#
(CBR) REFRESH in conventional DRAMs. This com -
m and is nonpersistent, so it m ust be issued each tim e
a refresh is req u ired . All active b an ks m u st b e
PRECHARGED prior to issuing an AUTO REFRESH com -
m and. The AUTO REFRESH com m and should not be
issued until the m inim um tRP has been m et after the
PRECHARGE com m and as shown in the operation sec-
tion.
The addressing is generated by the internal refresh
controller. This m akes the address bits “Don’t Care”
d u rin g an AUTO REFRESH com m an d . Th e 64Mb
SDRAM requires 4,096 AUTO REFRESH cycles every
64m s (tREF), regardless of width option. Providing a
distributed AUTO REFRESH com m and every 15.625µs
will m eet the refresh requirem ent and ensure that each
row is refreshed. Alternatively, 4,096 AUTO REFRESH
com m ands can be issued in a burst at the m inim um
cycle rate (tRC), once every 64m s.
Upon exiting the self refresh m ode, AUTO REFRESH
com m ands m ust be issued every 15.625µs or less as
both SELF REFRESH and AUTO REFRESH utilize the
row refresh counter.
SELF REFRESH
The SELF REFRESH com m and can be used to retain
data in the SDRAM, even if the rest of the system is
powered down. When in the self refresh m ode, the
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
©2003, Micron Technology, Inc.
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