1Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – IDD Specifications and Conditions
Table 19: IDD7 Measurement Loop (Continued)
16
17
18
3 × nFAW + nRRD
3 × nFAW + 2 × nRRD
3 × nFAW + 3 × nRRD
3 × nFAW + 4 × nRRD
3 × nFAW + 4 × nRRD + 1
Repeat sub-loop 11, use BA[2:0] = 5
Repeat sub-loop 10, use BA[2:0] = 6
Repeat sub-loop 11, use BA[2:0] = 7
D
1
0
0
0
0
7
0
0
0
0
0
–
19
Repeat cycle 3 × nFAW + 4 × nRRD until 4 × nFAW - 1, if needed
1. DQ, DQS, DQS# are midlevel unless driven as required by the RD command.
Notes:
2. DM is LOW.
3. Burst sequence is driven on each DQ signal by the RD command.
4. AL = CL-1.
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1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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