1Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – IDD Specifications and Conditions
Table 16: IDD4W Measurement Loop
0
1
WR
D
0
1
1
1
0
1
1
1
1
0
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
F
F
F
0
0
0
0
0
0
0
0
00000000
–
2
D#
D#
WR
D
–
3
–
0
4
00110011
5
–
–
–
6
D#
D#
7
1
2
3
4
5
6
7
8–15
16–23
24–31
32–39
40–47
48–55
56–63
Repeat sub-loop 0, use BA[2:0] = 1
Repeat sub-loop 0, use BA[2:0] = 2
Repeat sub-loop 0, use BA[2:0] = 3
Repeat sub-loop 0, use BA[2:0] = 4
Repeat sub-loop 0, use BA[2:0] = 5
Repeat sub-loop 0, use BA[2:0] = 6
Repeat sub-loop 0, use BA[2:0] = 7
1. DQ, DQS, DQS# are midlevel when not driving in burst sequence.
2. DM is LOW.
Notes:
3. Burst sequence is driven on each DQ signal by the WR command.
4. All banks open.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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