1Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – IDD Specifications and Conditions
Table 17: IDD5B Measurement Loop
0
0
1
REF
D
0
1
1
1
1
0
0
0
1
1
0
0
0
1
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
F
0
0
0
0
0
–
–
–
–
–
2
D
1a
3
D#
D#
4
1b
1c
1d
1e
1f
1g
1h
2
5–8
Repeat sub-loop 1a, use BA[2:0] = 1
Repeat sub-loop 1a, use BA[2:0] = 2
Repeat sub-loop 1a, use BA[2:0] = 3
Repeat sub-loop 1a, use BA[2:0] = 4
Repeat sub-loop 1a, use BA[2:0] = 5
Repeat sub-loop 1a, use BA[2:0] = 6
Repeat sub-loop 1a, use BA[2:0] = 7
9–12
13–16
17–20
21–24
25–28
29–32
33–nRFC - 1
Repeat sub-loop 1a through 1h until nRFC - 1; truncate if needed
1. DQ, DQS, DQS# are midlevel.
2. DM is LOW.
Notes:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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