欢迎访问ic37.com |
会员登录 免费注册
发布采购

MT41J256M4 参数 Datasheet PDF下载

MT41J256M4图片预览
型号: MT41J256M4
PDF下载: 下载PDF文件 查看货源
内容描述: DDR3 SDRAM MT41J256M4 â ????梅格32 ×4× 8银行MT41J128M8 â ????梅格16 ×8× 8银行MT41J64M16 â ???? 8梅格×16× 8银行 [DDR3 SDRAM MT41J256M4 – 32 Meg x 4 x 8 banks MT41J128M8 – 16 Meg x 8 x 8 banks MT41J64M16 – 8 Meg x 16 x 8 banks]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 214 页 / 2938 K
品牌: MICRON [ MICRON TECHNOLOGY ]
 浏览型号MT41J256M4的Datasheet PDF文件第42页浏览型号MT41J256M4的Datasheet PDF文件第43页浏览型号MT41J256M4的Datasheet PDF文件第44页浏览型号MT41J256M4的Datasheet PDF文件第45页浏览型号MT41J256M4的Datasheet PDF文件第47页浏览型号MT41J256M4的Datasheet PDF文件第48页浏览型号MT41J256M4的Datasheet PDF文件第49页浏览型号MT41J256M4的Datasheet PDF文件第50页  
1Gb: x4, x8, x16 DDR3 SDRAM  
Electrical Characteristics – IDD Specifications  
6a. When TC < 0°C: IDD2P0, IDD2P1 and IDD3P must be derated by 4%; IDD4R and IDD5W must  
be derated by 2%; and IDD6 and IDD7 must be derated by 7%.  
6b. When TC > 85°C: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, and IDD5B  
must be derated by 2%; IDD2Px must be derated by 30%.  
Table 21: IDD Maximum Limits – Rev. G  
Speed Bin  
Width  
IDD  
DDR3-1066  
DDR3-1333  
DDR3-1600  
DDR3-1866  
Units  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
Notes  
1, 2  
1, 2  
1, 2  
1, 2  
1, 2  
1, 2  
1, 2  
1, 2  
1, 2  
1, 2  
1, 2  
1, 2  
1, 2  
1, 2  
1, 2  
1, 2  
1, 2  
1, 2  
1, 2, 3,  
1, 4  
1, 2  
1, 2  
1, 2  
IDD0  
x4, x8  
x16  
60  
65  
70  
70  
75  
80  
85  
90  
IDD1  
x4, x8  
x16  
80  
85  
90  
90  
100  
110  
115  
120  
IDD2P0 (slow)  
IDD2P1 (fast)  
IDD2Q  
All  
12  
12  
12  
12  
All  
25  
30  
30  
35  
All  
35  
35  
40  
45  
IDD2N  
All  
35  
40  
45  
50  
IDD2NT  
x4, x8  
x16  
45  
50  
55  
60  
55  
60  
65  
75  
IDD3P  
IDD3N  
All  
30  
30  
35  
35  
x4, x8  
x16  
40  
40  
45  
50  
45  
45  
50  
55  
IDD4R  
x4, x8  
x16  
105  
125  
140  
155  
140  
165  
190  
215  
IDD4W  
x4, x8  
x16  
110  
125  
145  
160  
155  
180  
205  
230  
IDD5B  
IDD6  
IDD6ET  
IDD7  
All  
160  
165  
170  
175  
All  
8
10  
8
10  
8
10  
8
10  
All  
x4, x8  
x16  
195  
235  
245  
260  
235  
265  
300  
330  
IDD8  
All  
IDD2P0 + 2mA  
IDD2P0 + 2mA  
IDD2P0 + 2mA  
IDD2P0 + 2mA  
1. TC = 85°C; SRT and ASR are disabled.  
Notes:  
2. Enabling ASR could increase IDDx by up to an additional 2mA.  
3. Restricted to TC (MAX) = 85°C.  
4. TC = 85°C; ASR and ODT are disabled; SRT is enabled.  
5. The IDD values must be derated (increased) on IT-option and AT-option devices when op-  
erated outside of the range 0°C TC +85°C:  
6a. When TC < 0°C: IDD2P0, IDD2P1 and IDD3P must be derated by 4%; IDD4R and IDD5W must  
be derated by 2%; and IDD6 and IDD7 must be derated by 7%.  
6b. When TC > 85°C: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, and IDD5B  
must be derated by 2%; IDD2Px must be derated by 30%.  
PDF: 09005aef826aa906  
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
46  
‹ 2006 Micron Technology, Inc. All rights reserved.  
 复制成功!