1Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – DC and AC
4. VREFDQ(DC) may transition to VREFDQ(SR) and back to VREFDQ(DC) when in SELF REFRESH,
within restrictions outlined in the SELF REFRESH section.
5. VTT is not applied directly to the device. VTT is a system supply for signal termination re-
sistors. Minimum and maximum values are system-dependent.
Table 24: Input Switching Conditions
Parameter/Condition
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
DDR3-1866
DDR3-2133
Symbol
Unit
Command and Address
Input high AC voltage: Logic 1 @ 175mV
Input high AC voltage: Logic 1 @ 150mV
Input high AC voltage: Logic 1 @ 135 mV
Input high AC voltage: Logic 1 @ 125 mV
Input high DC voltage: Logic 1 @ 100 mV
Input low DC voltage: Logic 0 @ –100mV
Input low AC voltage: Logic 0 @ –125mV
Input low AC voltage: Logic 0 @ –135mV
Input low AC voltage: Logic 0 @ –150mV
Input low AC voltage: Logic 0 @ –175mV
VIH(AC175)min
VIH(AC150)min
VIH(AC135)min
VIH(AC125)min
VIH(DC100)min
VIL(DC100)max
VIL(AC125)max
VIL(AC135)max
VIL(AC150)max
VIL(AC175)max
175
150
–
175
150
–
–
–
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
135
125
100
–100
–125
–135
–
–
–
100
–100
–
100
–100
–
–
–
–150
–175
–150
–175
–
DQ and DM
Input high AC voltage: Logic 1
Input high AC voltage: Logic 1
Input high AC voltage: Logic 1
Input high DC voltage: Logic 1
Input low DC voltage: Logic 0
Input low AC voltage: Logic 0
Input low AC voltage: Logic 0
Input low AC voltage: Logic 0
VIH(AC175)min
VIH(AC150)min
VIH(AC135)min
VIH(DC100)min
VIL(DC100)max
VIL(AC135)max
VIL(AC150)max
VIL(AC175)max
175
150
–
–
150
–
–
–
mV
mV
mV
mV
mV
mV
mV
mV
135
100
–100
–135
–
100
–100
–
100
–100
–
–150
–175
–150
–
–
1. All voltages are referenced to VREF. VREF is VREFCA for control, command, and address. All
slew rates and setup/hold times are specified at the DRAM ball. VREF is VREFDQ for DQ
and DM inputs.
Notes:
2. Input setup timing parameters (tIS and tDS) are referenced at VIL(AC)/VIH(AC), not VREF(DC)
3. Input hold timing parameters (tIH and tDH) are referenced at VIL(DC)/VIH(DC), not VREF(DC)
.
.
4. Single-ended input slew rate = 1 V/ns; maximum input voltage swing under test is
900mV (peak-to-peak).
5. When two VIH(AC) values (and two corresponding VIL(AC) values) are listed for a specific
speed bin, the user may choose either value for the input AC level. Whichever value is
used, the associated setup time for that AC level must also be used. Additionally, one
VIH(AC) value may be used for address/command inputs and the other VIH(AC) value may
be used for data inputs.
For example, for DDR3-800, two input AC levels are defined: VIH(AC175),min and
V
IH(AC150),min (corresponding VIL(AC175),min and VIL(AC150),min). For DDR3-800, the address/
command inputs must use either VIH(AC175),min with tIS(AC175) of 200ps or VIH(AC150),min
with tIS(AC150) of 350ps; independently, the data inputs must use either VIH(AC175),min
with tDS(AC175) of 75ps or VIH(AC150),min with tDS(AC150) of 125ps.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
48
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