1Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – DC and AC
Electrical Specifications – DC and AC
DC Operating Conditions
Table 22: DC Electrical Characteristics and Operating Conditions
All voltages are referenced to VSS
Parameter/Condition
Supply voltage
Symbol
VDD
Min
1.425
1.425
–2
Nom
1.5
1.5
–
Max
1.575
1.575
2
Unit Notes
V
V
1, 2
1, 2
I/O supply voltage
VDDQ
II
Input leakage current
μA
Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 1.1V
(All other pins not under test = 0V)
VREF supply leakage current
IVREF
–1
–
1
μA
4
VREFDQ = VDD/2 or VREFCA = VDD/2
(All other pins not under test = 0V)
1. VDD and VDDQ must track one another. VDDQ must be ≤ VDD. VSS = VSSQ
.
Notes:
2. VDD and VDDQ may include AC noise of 50mV (250 kHz to 20 MHz) in addition to the
DC (0 Hz to 250 kHz) specifications. VDD and VDDQ must be at same level for valid AC
timing parameters.
3. VREF (see Table 23).
4. The minimum limit requirement is for testing purposes. The leakage current on the VREF
pin should be minimal.
Input Operating Conditions
Table 23: DC Electrical Characteristics and Input Conditions
All voltages are referenced to VSS
Parameter/Condition
Symbol
VIL
Min
VSS
Nom
n/a
Max
See Table 24
VDD
Unit Notes
VIN low; DC/commands/address busses
VIN high; DC/commands/address busses
Input reference voltage command/address bus
I/O reference voltage DQ bus
V
V
VIH
See Table 24
0.49 × VDD
0.49 × VDD
VSS
n/a
VREFCA(DC)
VREFDQ(DC)
VREFDQ(SR)
VTT
0.5 × VDD
0.5 × VDD
0.5 × VDD
0.5 × VDDQ
0.51 × VDD
0.51 × VDD
VDD
V
V
V
V
1, 2
2, 3
4
I/O reference voltage DQ bus in SELF REFRESH
Command/address termination voltage
(system level, not direct DRAM input)
–
–
5
1. VREFCA(DC) is expected to be approximately 0.5 × VDD and to track variations in the DC
level. Externally generated peak noise (noncommon mode) on VREFCA may not exceed
1% × VDD around the VREFCA(DC) value. Peak-to-peak AC noise on VREFCA should not ex-
Notes:
ceed 2% of VREFCA(DC)
.
2. DC values are determined to be less than 20 MHz in frequency. DRAM must meet specifi-
cations if the DRAM induces additional AC noise greater than 20 MHz in frequency.
3. VREFDQ(DC) is expected to be approximately 0.5 × VDD and to track variations in the DC
level. Externally generated peak noise (noncommon mode) on VREFDQ may not exceed
1% × VDD around the VREFDQ(DC) value. Peak-to-peak AC noise on VREFDQ should not ex-
ceed 2% of VREFDQ(DC)
.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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47
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