欢迎访问ic37.com |
会员登录 免费注册
发布采购

MT41J256M4 参数 Datasheet PDF下载

MT41J256M4图片预览
型号: MT41J256M4
PDF下载: 下载PDF文件 查看货源
内容描述: DDR3 SDRAM MT41J256M4 â ????梅格32 ×4× 8银行MT41J128M8 â ????梅格16 ×8× 8银行MT41J64M16 â ???? 8梅格×16× 8银行 [DDR3 SDRAM MT41J256M4 – 32 Meg x 4 x 8 banks MT41J128M8 – 16 Meg x 8 x 8 banks MT41J64M16 – 8 Meg x 16 x 8 banks]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 214 页 / 2938 K
品牌: MICRON [ MICRON TECHNOLOGY ]
 浏览型号MT41J256M4的Datasheet PDF文件第38页浏览型号MT41J256M4的Datasheet PDF文件第39页浏览型号MT41J256M4的Datasheet PDF文件第40页浏览型号MT41J256M4的Datasheet PDF文件第41页浏览型号MT41J256M4的Datasheet PDF文件第43页浏览型号MT41J256M4的Datasheet PDF文件第44页浏览型号MT41J256M4的Datasheet PDF文件第45页浏览型号MT41J256M4的Datasheet PDF文件第46页  
1Gb: x4, x8, x16 DDR3 SDRAM  
Electrical Specifications – IDD Specifications and Conditions  
Table 18: IDD Measurement Conditions for IDD6, IDD6ET, and IDD8  
IDD6: Self Refresh Current  
IDD6ET: Self Refresh Current  
Normal Temperature Range  
TC = 0°C to +85°C  
Extended Temperature Range  
TC = 0°C to +95°C  
IDD Test  
IDD8: Reset2  
Midlevel  
Midlevel  
N/A  
CKE  
LOW  
LOW  
External clock  
tCK  
tRC  
Off, CK and CK# = LOW  
Off, CK and CK# = LOW  
N/A  
N/A  
N/A  
N/A  
N/A  
tRAS  
N/A  
N/A  
N/A  
tRCD  
N/A  
N/A  
N/A  
tRRD  
N/A  
N/A  
N/A  
tRC  
N/A  
N/A  
N/A  
CL  
N/A  
N/A  
N/A  
AL  
N/A  
N/A  
N/A  
CS#  
Midlevel  
Midlevel  
Midlevel  
Midlevel  
Midlevel  
Enabled  
Enabled, midlevel  
N/A  
Midlevel  
Midlevel  
Midlevel  
Midlevel  
Midlevel  
Enabled  
Enabled, midlevel  
N/A  
Midlevel  
Midlevel  
Midlevel  
Midlevel  
Midlevel  
Midlevel  
Midlevel  
N/A  
Command inputs  
Row/column addresses  
Bank addresses  
Data I/O  
Output buffer DQ, DQS  
ODT1  
Burst length  
Active banks  
Idle banks  
SRT  
N/A  
N/A  
None  
N/A  
N/A  
All  
Disabled (normal)  
Disabled  
Enabled (extended)  
Disabled  
N/A  
ASR  
N/A  
1. “Enabled, midlevel” means the MR command is enabled, but the signal is midlevel.  
Notes:  
2. During a cold boot RESET (initialization), current reading is valid after power is stable  
and RESET has been LOW for 1ms; During a warm boot RESET (while operating), current  
reading is valid after RESET has been LOW for 200ns + tRFC.  
PDF: 09005aef826aa906  
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
42  
‹ 2006 Micron Technology, Inc. All rights reserved.  
 复制成功!