1Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – IDD Specifications and Conditions
Table 19: IDD7 Measurement Loop
0
1
ACT
RDA
D
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
–
00000000
–
0
1
2
3
Repeat cycle 2 until nRRD - 1
nRRD
ACT
RDA
D
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
1
1
1
0
0
0
0
1
0
0
0
0
F
F
F
0
0
0
–
nRRD + 1
00110011
–
nRRD + 2
nRRD + 3
Repeat cycle nRRD + 2 until 2 × nRRD - 1
Repeat sub-loop 0, use BA[2:0] = 2
Repeat sub-loop 1, use BA[2:0] = 3
2
3
2 × nRRD
3 × nRRD
4 × nRRD
D
D
1
1
0
0
0
0
0
3
0
0
0
F
0
–
–
4
4 × nRRD + 1
nFAW
Repeat cycle 4 × nRRD until nFAW - 1, if needed
Repeat sub-loop 0, use BA[2:0] = 4
Repeat sub-loop 1, use BA[2:0] = 5
Repeat sub-loop 0, use BA[2:0] = 6
Repeat sub-loop 1, use BA[2:0] = 7
5
6
7
8
nFAW + nRRD
nFAW + 2 × nRRD
nFAW + 3 × nRRD
nFAW + 4 × nRRD
nFAW + 4 × nRRD + 1
2 × nFAW
0
0
0
7
0
0
0
F
0
9
Repeat cycle nFAW + 4 × nRRD until 2 × nFAW - 1, if needed
ACT
RDA
D
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
F
F
F
0
0
0
–
2 × nFAW + 1
2 × nFAW + 2
2 × nFAW + 3
2 × nFAW + nRRD
2 × nFAW + nRRD + 1
2 × nFAW + nRRD + 2
2 × nFAW + nRRD + 3
2 × nFAW + 2 × nRRD
2 × nFAW + 3 × nRRD
2 × nFAW + 4 × nRRD
2 × nFAW + 4 × nRRD + 1
3 × nFAW
00110011
–
10
Repeat cycle 2 × nFAW + 2 until 2 × nFAW + nRRD - 1
ACT
RDA
D
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
1
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
–
00000000
–
11
Repeat cycle 2 × nFAW + nRRD + 2 until 2 × nFAW + 2 × nRRD - 1
Repeat sub-loop 10, use BA[2:0] = 2
12
13
Repeat sub-loop 11, use BA[2:0] = 3
D
1
0
0
0
0
3
0
0
0
0
0
–
14
15
Repeat cycle 2 × nFAW + 4 × nRRD until 3 × nFAW - 1, if needed
Repeat sub-loop 10, use BA[2:0] = 4
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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