1Gb: x4, x8, x16 DDR3 SDRAM
Commands
Figure 44: DLL Disable Mode to DLL Enable Mode
T0
Ta0
Ta1
Tb0
Tc0
Tc1
Td0
Te0
Tf0
Tg0
Th0
CK#
CK
CKE
Valid
t
DLLK
SRE1
SRX2
MRS3
MRS4
MRS5
Valid6
Command
NOP
NOP
7
t
8
t
9
t
t
t
CKSRE
CKSRX
XS
MRD
MRD
t
ODTLoff + 1 × CK
t
CKESR
ODT10
Indicates break
in time scale
Don’t Care
1. Enter SELF REFRESH.
2. Exit SELF REFRESH.
Notes:
3. Wait tXS, then set MR1[0] to 0 to enable DLL.
4. Wait tMRD, then set MR0[8] to 1 to begin DLL RESET.
5. Wait tMRD, update registers (CL, CWL, and write recovery may be necessary).
6. Wait tMOD, any valid command.
7. Starting with the idle state.
8. Change frequency.
9. Clock must be stable at least tCKSRX.
10. Static LOW in the case that RTT,nom or RTT(WR) is enabled; otherwise, static LOW or HIGH.
The clock frequency range for the DLL disable mode is specified by the parameter tCK
(DLL_DIS). Due to latency counter and timing restrictions, only CL = 6 and CWL = 6 are
supported.
DLL disable mode will affect the read data clock to data strobe relationship (tDQSCK)
but not the data strobe to data relationship (tDQSQ, tQH). Special attention is needed to
line up read data to the controller time domain.
Compared to the DLL on mode where tDQSCK starts from the rising clock edge AL + CL
cycles after the READ command, the DLL disable mode tDQSCK starts AL + CL - 1 cycles
after the READ command.
WRITE operations function similarly between the DLL enable and DLL disable modes;
however, ODT functionality is not allowed with DLL disable mode.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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125
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