1Gb: x4, x8, x16 DDR3 SDRAM
Input Clock Frequency Change
Figure 46: Change Frequency During Precharge Power-Down
Previous clock frequency
New clock frequency
Te0
Tc1
Td0
Td1
Te1
T0
T1
T2
Ta0
Tb0
Tc0
CK#
CK
tCH
tCL
tCH
tCL
tCH
tCL
b
tCH
tCL
b
b
b
b
b
tCK
tCK
tCK
b
tCK
b
b
tCKSRE
tCKSRX
tIH
tIH
tIS
tCKE
CKE
tIS
tCPDED
Command
NOP
Valid
Valid
NOP
NOP
NOP
NOP
MRS
NOP
Address
DLL RESET
tAOFPD/tAOF
tIH
tIS
tXP
ODT
DQS, DQS#
DQ
High-Z
High-Z
DM
tDLLK
Enter precharge
power-down mode
Frequency
change
Exit precharge
power-down mode
Indicates break
in time scale
Don’t Care
1. Applicable for both SLOW-EXIT and FAST-EXIT precharge power-down modes.
2. tAOFPD and tAOF must be satisfied and outputs High-Z prior to T1 (see On-Die Termina-
tion (ODT) (page 193) for exact requirements).
Notes:
3. If the RTT,nom feature was enabled in the mode register prior to entering precharge
power-down mode, the ODT signal must be continuously registered LOW, ensuring RTT
is in an off state. If the RTT,nom feature was disabled in the mode register prior to enter-
ing precharge power-down mode, RTT will remain in the off state. The ODT signal can
be registered LOW or HIGH in this case.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
128
2006 Micron Technology, Inc. All rights reserved.
MICRON [ MICRON TECHNOLOGY ]
