1Gb: x4, x8, x16 DDR3 SDRAM
Commands
DLL Disable Mode
If the DLL is disabled by the mode register (MR1[±] can be switched during initialization
or later), the DRAM is targeted, but not guaranteed, to operate similarly to the normal
mode, with a few notable exceptions:
• The DRAM supports only one value of CAS latency (CL = 6) and one value of CAS
WRITE latency (CWL = 6).
• DLL disable mode affects the read data clock-to-data strobe relationship (tDQSCK),
but not the read data-to-data strobe relationship (tDQSQ, tQH). Special attention is
required to line up the read data with the controller time domain when the DLL is dis-
abled.
• In normal operation (DLL on), tDQSCK starts from the rising clock edge AL + CL
cycles after the READ command. In DLL disable mode, tDQSCK starts AL + CL - 1 cy-
cles after the READ command. Additionally, with the DLL disabled, the value of
tDQSCK could be larger than tCK.
The ODT feature (including dynamic ODT) is not supported during DLL disable mode.
The ODT resistors must be disabled by continuously registering the ODT ball LOW by
programming RTT,nom MR1[9, 6, 2] and RTT(WR) MR2[1±, 9] to ± while in the DLL disable
mode.
Specific steps must be followed to switch between the DLL enable and DLL disable
modes due to a gap in the allowed clock rates between the two modes (tCK [AVG] MAX
and tCK [DLL_DIS] MIN, respectively). The only time the clock is allowed to cross this
clock rate gap is during self refresh mode. Thus, the required procedure for switching
from the DLL enable mode to the DLL disable mode is to change frequency during self
refresh:
1. Starting from the idle state (all banks are precharged, all timings are fulfilled, ODT
is turned off, and RTT,nom and RTT(WR) are High-Z), set MR1[±] to 1 to disable the
DLL.
2. Enter self refresh mode after tMOD has been satisfied.
3. After tCKSRE is satisfied, change the frequency to the desired clock rate.
4. Self refresh may be exited when the clock is stable with the new frequency for
tCKSRX. After tXS is satisfied, update the mode registers with appropriate values.
5. The DRAM will be ready for its next command in the DLL disable mode after the
greater of tMRD or tMOD has been satisfied. A ZQCL command should be issued
with appropriate timings met.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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