1Gb: x4, x8, x16 DDR3 SDRAM
Commands
Figure 42: Refresh Mode
T0
Ta0
Ta1
T4
T2
T3
Tb0
Tb1
Tb2
T1
CK#
CK
tCK
tCH
tCL
5
5
5
5
CKE
Valid
Valid
Valid
2
REF
1
1
1
5
5
Command
NOP
PRE
NOP
NOP
REF
NOP
NOP
NOP
ACT
Address
A10
RA
RA
All banks
One bank
3
BA[2:0]
Bank(s)
BA
4
DQS, DQS#
4
DQ
4
DM
tRP
tRFC (MIN)
tRFC2
Indicates break
in time scale
Don’t Care
1. NOP commands are shown for ease of illustration; other valid commands may be possi-
ble at these times. CKE must be active during the PRECHARGE, ACTIVATE, and REFRESH
commands, but may be inactive at other times (see Power-Down Mode (page 183)).
Notes:
2. The second REFRESH is not required, but two back-to-back REFRESH commands are
shown.
3. “Don’t Care” if A10 is HIGH at this point; however, A10 must be HIGH if more than one
bank is active (must precharge all active banks).
4. For operations shown, DM, DQ, and DQS signals are all “Don’t Care”/High-Z.
5. Only NOP and DES commands are allowed after a REFRESH command and until tRFC
(MIN) is satisfied.
SELF REFRESH
The SELF REFRESH command is used to retain data in the DRAM, even if the rest of the
system is powered down. When in self refresh mode, the DRAM retains data without ex-
ternal clocking. Self refresh mode is also a convenient method used to enable/disable
the DLL as well as to change the clock frequency within the allowed synchronous oper-
ating range (see Input Clock Frequency Change (page 120)). All power supply inputs
(including VREFCA and VREFDQ) must be maintained at valid levels upon entry/exit and
during self refresh mode operation. VREFDQ may float or not drive VDDQ/2 while in self
refresh mode under the following conditions:
• VSS < VREFDQ < VDD is maintained
• VREFDQ is valid and stable prior to CKE going back HIGH
• The first WRITE operation may not occur earlier than 512 clocks after VREFDQ is valid
• All other self refresh mode exit timing requirements are met
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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