1Gb: x4, x8, x16 DDR3 SDRAM
Commands
Figure 43: DLL Enable Mode to DLL Disable Mode
T0
T1
Ta0
Ta1
Tb0
Tc0
Td0
Td1
Te0
Te1
Tf0
CK#
CK
1
CKE
Valid
Valid1
MRS2
SRE3
SRX4
MRS5
Command
NOP
NOP
NOP
NOP
t
6
t
7
t
8
t
t
MOD
XS
MOD
CKSRE
CKSRX
t
CKESR
ODT9
Valid1
Indicates break
in time scale
Don’t Care
1. Any valid command.
Notes:
2. Disable DLL by setting MR1[0] to 1.
3. Enter SELF REFRESH.
4. Exit SELF REFRESH.
5. Update the mode registers with the DLL disable parameters setting.
6. Starting with the idle state, RTT is in the High-Z state.
7. Change frequency.
8. Clock must be stable tCKSRX.
9. Static LOW in the case that RTT,nom or RTT(WR) is enabled; otherwise, static LOW or HIGH.
A similar procedure is required for switching from the DLL disable mode back to the
DLL enable mode. This also requires changing the frequency during self refresh mode
(see Figure 44 (page 125)).
1. Starting from the idle state (all banks are precharged, all timings are fulfilled, ODT
is turned off, and RTT,nom and RTT(WR) are High-Z), enter self refresh mode.
2. After tCKSRE is satisfied, change the frequency to the new clock rate.
3. Self refresh may be exited when the clock is stable with the new frequency for
tCKSRX. After tXS is satisfied, update the mode registers with the appropriate val-
t
ues. At a minimum, set MR1[±] to ± to enable the DLL. Wait MRD, then set MR±[8]
to 1 to enable DLL RESET.
4. After another tMRD delay is satisfied, update the remaining mode registers with
the appropriate values.
5. The DRAM will be ready for its next command in the DLL enable mode after the
greater of tMRD or tMOD has been satisfied. However, before applying any com-
mand or function requiring a locked DLL, a delay of tDLLK after DLL RESET must
be satisfied. A ZQCL command should be issued with the appropriate timings met.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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